logic of opening pmos and nmos simultaniosly

[john23]

Hello, node "e" is rising after the pulses stabilize.
There are PMOS and NMOS which need to be open simultaniosly.
What is the logic in using NPN with a diode to open these mosfets?
Also why M1 has 100uF capacitor at the gate while M2 has only resistors?
Thanks.

[PCB.Wiz]

Hello, node "e" is rising after the pulses stabilize.
There are PMOS and NMOS which need to be open simultaniosly.
What is the logic in using NPN with a diode to open these mosfets?

That looks to be a kludge attempt to match the FET threshold with the 1.2V transistor + diode threshold.
Once that is reached, the top PMOS turn on rapidly.
It is approximate only, and roughly matches one point of the curve, without much consideration of speed or slopes, or part variations.
That may be 'good enough' in this application.

[Andy Chee]

Is this a continuation of your same project?

https://www.eevblog.com/forum/projects/analog-logic-of-comprator-based-analog-stabilier-pulse-circuit/msg5674515/#msg5674515

https://www.eevblog.com/forum/projects/converting-power-supply-signal-into-pulse-signal/msg5670163/#msg5670163

https://www.eevblog.com/forum/projects/fixing-design-for-simultanios-excitation-of-a-sequencer/msg5643509/#msg5643509

https://www.eevblog.com/forum/projects/bjt-invertive-switching-logic-question/msg5624647/#msg5624647

https://www.eevblog.com/forum/projects/pure-dc-voltage-delay-mechanism-question/msg5621559/#msg5621559

[john23]

Hello PCB.Wiz,Yes We need to match the  absolute vslue of Vgs on bot mosfets at a certain time point, so they open at a certaint ime point.
We have node e starting to rise.
Its going to  NPN ,whic has a resitor form one side the a diode on the other side.
NPN is just a valve to create certain Ic current.
Also the diode is touchin the drain.
What is the point in this?
Thanks.

[PCB.Wiz]

Also the diode is touchin the drain.
What is the point in this?

That now acts as a AND gate, so the drain must be low and the cap > 1.2V before the upper FET starts.
ie it sequences the rails so the negative rail always comes up first.
The exact delays depend on the lower mosfet threshold.
Spice will easily show you all of this. Change a few things and see for yourself.