In the basic class-D amplifiier topology that you're considering, trying to coerce the input signal to have an amplitude close to full-scale (according to your input stage) doesn't actually make sense, because it would drive your amplifier at "full volume". Unless you have other means of controlling the output level, it would be exactly like considering driving a typical analog amplifier at the maximum level. That doesn't make sense from an usability point of view. Or you would have to be able to adjust the output volume another way, such as modulating the power supplies of the output stage (which frankly I have rarely seen).
It would be like willing to put an AGC in front of just any ADC for the sake of optimizing the SNR.
I get your concern though, but I don't think I have ever seen any class-D amplifier (at least for audio) taking this approach to optimize the SNR. To optimize it, you will need to generate a very clean triangle signal which is not that trivial, and then use a very fast comparator, and beefy gate drivers.
Unless you actually want to compress the signal purposefully, using an AGC is horrible for an audio amp. You may slightly improve the SNR but will dramatically decrease the dynamic range. A typical audio signal is nothing like a constant amplitude signal.
You just need a small preamp stage as a front-end of your amplifier and an attenuator to adjust the volume. Just like any other amplifier.
For the typical "line level", you can refer to the following:
https://en.wikipedia.org/wiki/Line_levelOf course many devices do not respect this to the letter. But a ~1Vpp signal gives you an idea of what to expect.
For a 3.3V input stage, I would typicallly use a x2 to x3 gain (or maybe up to x10 if I wanted to accomodate for lower output levels) and put the attenuation stage before the gain stage. The attenuation stage will typically be your volume control.
If I were to design a class-D amplifier from scratch, nowadays I would personally take a full-digital approach (digital input - sigma-delta modulator), but I admit it's a bit more involved. That can be done on a small FPGA with pretty good results. Obviously there are many ready-to-use ICs for that, but that's outside of the scope of designing the thing yourself.