Questions on designing Fwd/Rev 12V DC motor controller for 80A typ (200A peak)

[Berni]

Here's an example of the sort of thing i'm talking about.
https://www.digikey.com/en/products/detail/on-semiconductor/FDMT80040DC/7356044
420A continuous 2644A peak
Power dissipation 156W
But it's in a tiny 8x8mm package.
It gives some pcb layout pad size info in the DS but still, seems a little crazy.
I suspect it's intended for like 1U or 2U servers with crazy amounts of airflow.

That is very impressive indeed, but be careful with the numbers you find on the first page of the datasheet.

While it might be possible to put 400A continuously trough it doing so according to the resistance of say 0.8 mOhm (Add a bit for drop due to channel saturation, temp rise etc) you end up dissipating about 130W of heat so if you cool it from the bottom to 25°C it experiences a drop of 0.8 °C/W so the die ends up at about 130°C. It is really a best case possible laboratory scenario. To achieve this they likely soldered the mosfet directly to a fist sized block of copper that is used for both cooling and current transfer. If we assume this copper to be about 1cm around the transistor this gives an additional 0.26 °C/W. So due to the thermal resistance of the copper and extra resistive losses in the connection, this adds another 40°C temp rise, so to get the actual transistor to 25°C the outside of the block needs to be cooled to -15°C. They likely did this by forcefully pushing boiling refrigerant through cooling channels in that copper block.

Safe to say you will not be able to recreate anywhere near such conditions in the actual product. However, the engineers do end up including real world achievable thermal resistance numbers and sneaking it past the marketing department into the datasheet. The actual real world numbers for thicker copper 2oz PCB with lots of airflow is 26°C/W or 38°C/W with no forced airflow. So punching in the numbers for a reasonable 75°C ambient you get a power dissipation of 2W before the transistor blows up and this lets it pass about 50A max. However, this is still assuming your copper traces are an electrical superconductor, so on an actual 2oz PCB the traces will add additional heating and make it blow up even sooner.

If you add heatsinking you can bring the thermal resistance down to 9°C so this gets you 8W of thermal dissipation and so a max current of about 100A. If you have a good aluminium core board you might be able to push it up to 15W of dissipation so about 140A. So even the best case real-world scenario is not even close to 400, but is still very impressive for such a little mosfet.

You can parallel mosfets when in switching applications reasonably safely, just make sure they see the same resistance both thermally and electrically so that they share nicely.

[Psi]

This product is almost done but I just wanted to post this scope image and confirm my understanding is correct

This is the voltage across the worst mosfet (furthest away from TVS/CAP).
It's the high side mosfet at switch-off with the maximum loading I should ever see.
It looks to me like the TVS is clamping the back EMF nicely at 33V. (The TVS used (LNBTVS4-222S) Vclamp is 33.2V max (10/1000 µs).
There's also a flat area around 22V which matches the breakdown voltage of the TVS, so I assume it corresponds to that.

The mosfet's are 40V so there's 7V before that happens at worst case.
So my question is, does this waveform all make sense for a TVS correctly preventing back EMF that might damage the mosfet.

[T3sl4co1l]

What was that then, 30A at the transistor? 60?

If 60, that implies an average dI/dt of 170A/us, and an overshoot of 10V implies L = (10V)/(170A/us) = 60nH between the transistor and TVS.

Seems kind of high?  I wonder if dI/dt is falling by that point.

During the clamping period, it's what 8V above baseline, for about 90ns, or 0.72uVs... but this depends on the load, supply and TVS inductances, and how much is left after the transistor's switched off, so it's not apparent what current or inductance is in play here.

Tim

[moffy]

I couldn't find on the data sheet a continuous power rating for the device. I would be concerned with exceeding the continuous power  dissipation, but you don't know what that is for the device. I personally feel a little uncomfortable with 40v MOSFETs and a repetitive 33v clamp, not a lot of headroom, I would go for higher voltage rated MOSFETs just for peace of mind, but that's my paranoia speaking.

[Psi]

What was that then, 30A at the transistor? 60?

If 60, that implies an average dI/dt of 170A/us, and an overshoot of 10V implies L = (10V)/(170A/us) = 60nH between the transistor and TVS.

Seems kind of high?  I wonder if dI/dt is falling by that point.

During the clamping period, it's what 8V above baseline, for about 90ns, or 0.72uVs... but this depends on the load, supply and TVS inductances, and how much is left after the transistor's switched off, so it's not apparent what current or inductance is in play here.

Tim

Should be 20-30A through the mosfet.

[Psi]

I couldn't find on the data sheet a continuous power rating for the device. I would be concerned with exceeding the continuous power  dissipation, but you don't know what that is for the device. I personally feel a little uncomfortable with 40v MOSFETs and a repetitive 33v clamp, not a lot of headroom, I would go for higher voltage rated MOSFETs just for peace of mind, but that's my paranoia speaking.

In this application the situation which causes the spike is reoccurring in the human timescale of seconds to hours, even weeks. There is plenty of time for cooldown so the pulse power rating is more relevant than continuous.

I could try some 18V TVS diodes instead of 22V and see what I get then, that would drop it a little lower.

[moffy]

If it is non repetitive, what is causing the spike? Perhaps an RC snubber across the MOSFET might help absorb some energy and reduce the peak.

[T3sl4co1l]

Take note of the power level here: it will have to be quite a large capacitor, and small resistor, to be able to do that.  Switching loss will be greatly impacted at lighter load.

And more importantly, the capacitors will be so (physically) large that it's even less practical to interleave them with the transistors!

Yes, I have no problem with the spike, if that's worst-case already then who cares, done and done; if current can be a good 30% or so higher then that should be enough to push it into avalanche, but even that isn't fatal due to the low repeat rate.  But do mind it is a wear mechanism, it won't last forever that way.

Tim

[Psi]

if current can be a good 30% or so higher then that should be enough to push it into avalanche, but even that isn't fatal due to the low repeat rate.  But do mind it is a wear mechanism, it won't last forever that way.

Yeah.

Perhaps under a output dead short scenario. But given the product application this is unlikely in the products entire life.

The circuit does have hardware overcurrent trip using the comparator in the MCU which has hardware comparator output pin driving fets which short the gate optocoupler LEDs to GND.

[moffy]

Did a quick sim in LTSpice and 0.5R/220nf was pulling about 9A for a similar edge. Thing about RC's, if the ratings are not exceeded they last.

[Psi]

What is the usual technique to measure the peak current through a TVS diode?
Obviously you cannot add anything in series or the reading wont be correct.

Some sort of hall effect current probe?

The current TVS i'm using (LNBTVS4-222S) is 3 kW (10/1000 µs) 22.5 kW (8/20 µs).
It's probably way overkill, but I don't know how to figure out the ideal TVS.
(Other than trying smaller and smaller TVS diodes until one fails then add a good amount of margin on top of that one)

[T3sl4co1l]

If you can get a loop around it, a Rogowski coil will do.

With a pulse under 200ns width and up to 200A at 30V = 6kW, you're delivering well under the 22.5kW rated for a 100 times longer pulse.

This one doesn't, but others show a power vs. time curve, which will be helpful in selecting minimal parts.  I'd just as well stick with the SMC as it's a wider body, so potentially lower inductance.

Tim