EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: promach on June 18, 2021, 09:55:23 am
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Could anyone explain on "Obviously, the compensation capacitance CC does not connect Drain to Gate directly around output transistor M10. It takes a path through cascode device M6, in order to avoid a positive zero. " ?
(https://i.imgur.com/PqojzkV.png)
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You need to be a bit more explicit in what you're asking. I take it, but I'm not sure, that you're asking:
- What is a "cascode"?
- What is a "positive zero"?
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Looks like feedforward zero and Ahuja compensation.
edit
I never really understood the problem of FF zero either. So I played with SPICE and got the result below. It appears in disturbingly idealized circuits and apparently boils down to conductance of Cc exceeding gain device transcundactance and taking over driving the output.
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@magic I am confused with how Ahuja compensation (https://milindsweb.amved.com/docs/Ahuja_Compensation_Paper.pdf#page=3) works ?
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Cascode M6 ensures that the left side of Cc sees a (mostly) constant voltage. Hence Cc current is only dependent on output voltage swing and no current passes Cc due to M10 gate drive waveform.
BTW, I could swear that "Analog Design Essentials" sounds like a sort of book that should explain all of that.
If they say it's obvious, it's probably because the topic has already been :horse: in earlier chapters.
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For those interested in Ahuja compensation, Baker's uses "indirect compensation" in his book : CMOS: Circuit Design, Layout, and Simulation (http://libgen.li/item/index.php?md5=C0217E0E58A94DF75379678BA11D367B) , see page 813, 814 and 815
(https://i.imgur.com/XqJSEUr.png)
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I am now working on the actual mosfet circuitry implementation (https://gist.github.com/promach/183703eacba9de7eba2f9d91aa9e4ce1), the circuit is not working yet.
Note: I will decrease the Vin+ and Vin- voltage amplitude afterwards.
(https://i.imgur.com/ZTp8kin.png)
(https://i.imgur.com/rJXbKty.png)
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Your PMOS symbols are upside down, dunno if the model is symmetric.
Common LTspice beginner gotcha |O
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What do you mean by "Your PMOS symbols are upside down" ?
I have updated the mosfet circuitry (https://gist.github.com/promach/183703eacba9de7eba2f9d91aa9e4ce1#file-sub-1_volt_ota-asc), and the OTA circuit seems to be working fine in transient analysis.
However, why does the AC analysis plot look so bad ?
(https://i.imgur.com/Yp7cCzR.png)
(https://i.imgur.com/KeEoeGp.png)
(https://i.imgur.com/N2xyZ7w.png)
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Is the switch labelled as 2n related to CMFB since CMFB is required for all differential OTA circuit structure (https://people.engr.tamu.edu/spalermo/ecen474/lecture18_ee474_ota_cmfb.pdf#page=5) ?
(https://i.imgur.com/nhLbpWa.png)
(https://i.imgur.com/PbIHSmH.png)
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What do you mean by "Your PMOS symbols are upside down" ?
Exactly that. You've connected them with the sources at the bottom and the drains at the top connected to the positive rail. Convention when drawing "L" shaped gates is for the gate to come out on the source side of the channel.
(https://external-content.duckduckgo.com/iu/?u=https%3A%2F%2Fi.stack.imgur.com%2FUD5KS.jpg&f=1&nofb=1)
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Do not worry about the mosfet direction or the symbol itself.
I have used these PMOS and NMOS in previous projects without any issues.
By the way, the following transient analysis results seems a bit strange.
(https://i.imgur.com/zQnFfUN.png)
(https://i.imgur.com/ZThaTkW.png)