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Questions on Sub-1 Volt OTA

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Could anyone explain on "Obviously, the compensation capacitance CC does not connect Drain to Gate directly around output transistor M10. It takes a path through cascode device M6, in order to avoid a positive zero. " ?

You need to be a bit more explicit in what you're asking. I take it, but I'm not sure, that you're asking:

* What is a "cascode"?
* What is a "positive zero"?

Looks like feedforward zero and Ahuja compensation.

I never really understood the problem of FF zero either. So I played with SPICE and got the result below. It appears in disturbingly idealized circuits and apparently boils down to conductance of Cc exceeding gain device transcundactance and taking over driving the output.

@magic  I am confused with how Ahuja compensation works ?

Cascode M6 ensures that the left side of Cc sees a (mostly) constant voltage. Hence Cc current is only dependent on output voltage swing and no current passes Cc due to M10 gate drive waveform.

BTW, I could swear that "Analog Design Essentials" sounds like a sort of book that should explain all of that.
If they say it's obvious, it's probably because the topic has already been :horse: in earlier chapters.


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