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read endurance for flash memory?
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FrankBuss:
I plan to use this SPI flash memory in combination with a FPGA and execute code from it, reading it with 100 MHz, so I can execute 32 bit RISC-V instructions with about 2 MHz worst case, and more than 10 MHz for consecutive instructions (using the quad read feature, with no cache, maybe even up to 25 MHz with the compressed instruction set). But I can't find a limit how often it can be read, is there a limit? For NAND flash there is an interesting read disturb effect: If you read one cell too often, it can change the value of neighbor cells. But I guess the SPI flash uses NOR flash, at least this is mentioned in the datasheet a few times. Is this a problem for NOR flash as well, or are there other problems when reading this chip continuously with 100 MHz?
FrankBuss:
Found an answer on stackexchange:

https://electronics.stackexchange.com/questions/162415/will-reading-serial-flash-memory-wear-it-out

Someone was asking for problems with the SPI flash memory IC SST25VF, which is NOR flash, and the accepted answer says it has read disturb problems. Of course, it doesn't mean that it must be right :)
DC1MC:
It isn't the defect is problem for NAND flash, as even the linked article said, but then again everything but the price is a problem for the NAND flash  ;D.

 
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