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Reading and understanding this schematic [Discussion]

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XaviPacheco:
Just a brief question that came to my mind now. As the capacitor after the rectifier is just 22 nF in the first schematic, does this mean the inrush current is harmless, right?

magic:
The FET is a "source follower". Its source voltage follows gate voltage (minus a few volts) because if source voltage falls, source-gate voltage increases and the FET turns on.
Its gate is held 43V above negative rail by R1/D1 so you get about 40V at source.

The power board doesn't care whether its output is -13V/27V or 0V/40V. It would work exactly the same.

XaviPacheco:

--- Quote from: magic on June 17, 2019, 10:36:52 pm ---The FET is a "source follower". Its source voltage follows gate voltage (minus a few volts) because if source voltage falls, source-gate voltage increases and the FET turns on.
Its gate is held 43V above negative rail by R1/D1 so you get about 40V at source.

The power board doesn't care whether its output is -13V/27V or 0V/40V. It would work exactly the same.

--- End quote ---

Thank you. At last, for me to understand better, I would like to prove these value by doing some quick math like KVL/KCL. How did you calculate the 15~20 mA? Maybe if I simulate it I can be more clear. Someone told me that in order to switch the FET, the V+ point should be grounded, which is what the SCR does in the second schematic, it connects +V to -13V. When the coil is activated, the main line power (480 VAC) is removed, and the circuit shuts down.

I would happy if I'm able to prove (mathematically) the +27V. Yes, I know you already told me, but if I write some equations to show it, I would be more clear.

dmills:
When you short the V+ and -13V point together the mosfet current rises (because the load in the source is now ~5R plus a diode drop or two), this  causes the coil current to rise until either it is limited by the 5.1R resistor robbing Vgs or by the coil resistance.

The trip coil will be designed to not release the trip when only the idle current is flowing but to cause the breaker to drop when this much larger current flows.

This sort of thing is very typical of highly cost optimised design.

Regards, Dan.

XaviPacheco:

--- Quote from: dmills on June 19, 2019, 10:15:05 am ---When you short the V+ and -13V point together the mosfet current rises (because the load in the source is now ~5R plus a diode drop or two), this  causes the coil current to rise until either it is limited by the 5.1R resistor robbing Vgs or by the coil resistance.

The trip coil will be designed to not release the trip when only the idle current is flowing but to cause the breaker to drop when this much larger current flows.

This sort of thing is very typical of highly cost optimised design.

Regards, Dan.

--- End quote ---

Why is this a highly cost optimized design? What are other things take into account in optimized designs?

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