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Reading and understanding this schematic [Discussion]
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XaviPacheco:
See attachments Power1 and Power2. I'm doing some reverse engineering and I'm trying to understand the functionality. The two schematics are located in different PC boards that are interconnected. As you can see, for example, the +27V point comes out from Power1 schematic and connects with Power2 schematic where it's feeding a LM317 regulator. I'm not showing the whole circuitry. There's another control circuit which processes a signal coming from a current transformer. Additional information: the input line to line voltage ranges from 220 to 480 VAC. So based on the schematics:

 1) How are the +27 and -13 voltages generated? I'm kind of confused as it seems like in Power1 schematic the reference is NOT zero volts. I know there should be a trick with the zener diodes.
 2) How is the FET turned on? Is it through the +V point which connects with -13V through the SCR in Power2 schematic?
 3) At the drain of the FET, there is a freewheeling diode for the coil and a stack of three TVS diodes in series (not sure why three).
 4) At last, I want to understand better the setup at the source of the FET

 I'm just asking for few hints that help me interpret the circuit in a better way.

 What improvements would you make to this circuit?
Psi:
For the LM317 the 13V zener adds 13V, canceling out the -13V to zero.
Next the 12V zener raises the output by 12V.
Then you have the internal 1.25V reference of the LM317.
Hence the final output voltage is 12+1.25 = 13.25V with respect to what he is calling GND.

Note: This designer has chosen to GND a mid point in the output voltage in order to get the -13V. He could just as well have called that point GND.
magic:
M1 is turned on by R1 charging its gate towards positive rail.
R2+R3 and D2 implement current limiting - if current reaches 15~20mA, there is almost 10V loss across R2+R3 and D2 discharges M1 gate to a voltage barely above M1 source, limiting further current flow through M1.
D1 limits M1 gate to 43V above the negative rail, so for M1 to conduct at all, about 40V above the negative rail must be at its source. Since the negative rail is regulated by zener D3 to -13, that makes about 27V at the output of M1 if there is no load current across R3.
The SCR appears to be a crowbar which shorts M1 output to ground to shutdown downstream circuitry.
Not sure what's the point of the choke.
XaviPacheco:
D3 in schematic 1 is the freewheeling diode for the coil I think. This coil should be activated when commanded by the control circuit (that I'm not showing) to trip something. The control circuit is being powered by the 13.25V coming out of the LM317 and uses both references -13V, and 0V. I was trying to see what's the origin of signal the FET needs to get activated. How can this circuit be improved? Also, what's the point of the three TVS diodes in series? The reverse breakdown voltage is about 900V.
XaviPacheco:

--- Quote from: magic on June 14, 2019, 02:16:15 pm ---M1 is turned on by R1 charging its gate towards positive rail.
R2+R3 and D2 implement current limiting - if current reaches 1.5~2A, there is almost 10V loss across R2+R3 and D2 discharges M1 gate to a voltage barely above M1 source, limiting further current flow through M1.
D1 limits M1 gate to 43V above the negative rail, so for M1 to conduct at all, about 40V above the negative rail must be at its source. Since the negative rail is regulated by zener D3 to -13, that makes about 27V at the output of M1 if there is no load current across R3.
The SCR appears to be a crowbar which shorts M1 output to ground to shutdown downstream circuitry.
Not sure what's the point of the choke.

--- End quote ---

So in the first circuit the 0V reference is brought down to -13V by the second circuit?
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