Question about high speed PCB design

[IO390]

I'm working on a MIPI switch. This is the second iteration, the previous version used a tiny BGA package (0.4mm pitch) which was all well and good however I had to use an HDI spec PCB, which cost an arm and a leg.

That PCB had problems with signal integrity, partially because I forgot to add the vias to the GND pin on the chip... I don't want to make such an expensive mistake again, and prototyping with HDI PCBs is not really within my budget at present.

As a result, I want to use a non BGA package so I can design within normal, say JLCPCB design rules. The MIPI device is 4 lanes and the only dedicated 4 lane MIPI switches available are in BGA packages, such as TS5MP645.

The next best idea I could come up with is to use 2x FSA642 which will only do two lanes and a clock each. So one chip will do two lanes and the clock, and another chip for the other two lanes.

Here is my PCB design so far. Connectors are Hirose DF56 series. I've set up the impedance matching on the differential traces as per the JLCPCB impedance calculator. Length is matched to about +/- 0.1mm. Am I totally off the mark and this will result in total failure, or is this about right for high speed differential pairs? I've read as many app notes as I can on high speed layouts but I'm still guessing really. Any input would be gratefully received.

[dmg]

I assume this is at least a 4 layers board, right?

There are a couple of things that I see at first glance. First one is that you should place the intra-pair length-matching meanders as close as possible to where the length mismatch occurs. In your case you have a huge length mismatch at the top connector, so you should adjust the length of the shortest trace in the pair as close as possible to the connector exit. In your case it would be better to use a large meander rather than several small ones to compensate the length as quickly as possible.

Also, as you are forced to have your pairs uncoupled for quite a bit of length, you should aim for a loosely coupled pair geometry. I mean, you can get a 100 ohm differential impedane with two tightly coupled 70 ohm traces, or you can get it with two very loosely coupled 50-ish ohm traces. In your case, the latter would be better, making your layout more insensitive to the uncoupling that occurs near the top connector. This also helps with via design. Tightly coupled pairs require good via design to avoid discontinuities (antipad and pad diameters and such), while loosely coupled are more insensitive and will do fine with more carelessly designed vias. You'll have to increase the antipad size for your vias anyway to reduce their stray capacitance and minimize impedance discontinuities.

Also, every time you switch layers AND reference plane (in your case you switch your pairs from top to bottom, so there's a reference plane change unless you're using a 2 layer board which you shoudn't) you have to add ground stitching vias near the layer switching vias to provide a good path for the return currents.

Finally, sometimes you need to create voids in the reference plane immediately below connector or component pads if they are much wider than the high speed traces to reduce the parasitic capacitance and minimice discontinuities. This becomes more critical the higher in Gbps you go.

As long as you're not going past ~10Gbps per lane it should be """"relatively"""" easy to get working. Past that and you'll have to take into account prepreg weavings, copper roughness, your layer transitions no longer work as "lumped" discontinuities and many other aspects.

[IO390]

I assume this is at least a 4 layers board, right?

Thank you for the detailed reply.

This will indeed be a 4 layer board. I actually made a test board for other reasons, but I intentionally paid very little attention to the MIPI routes, pictured below. This was a 2 layer board and the MIPI traces are about 15mm long. This board introduces another cable into the system as well and it all worked fine. Interestingly I was able to add about 20mm of length mismatch (the enamelled wire) to one of the lanes before the data became unreadable.

With regards to the data rate, the clock is at about 700MHz max (4k CSI sensor that I'm switching) so I presume the FSA642 switch is up to the task.

I see what you're saying about using 50 ohm stripline instead of the 100 ohm pair. Do you mean this would be best on the top connector with the large mismatch, or in general for this design?

Would it be better to perhaps bring the traces from the top connector to the other side of the board using vias underneath the connector body, as per the lower connector? This could avoid the dramatic length mismatch between the traces in each pair.


The routing for the third connector is supposed to be on an inner layer, though it would still have uninterrupted ground planes on both sides. I understand the impedance of the trace changes accordingly.

[Twoflower]

How about putting the connectors on the other side of the PCB at the cost of having all signals one via instead of some. As it seems that you use vias anyway. The two sided approach allow you to make the lane routing more symmetric at the connectors. Route the pair between the rows of the connector, place the vias that way that you only need to go straight up and down the same distance but also to keep the pair together as long as possible.

Edit: Is the pinning fixed or is the pinning of the connectors your own design? Usually the pair of a signal should be next to each other and not opposite. Because of the problems you're facing: Big differences in length, long not coupled traces.

[IO390]

How about putting the connectors on the other side of the PCB at the cost of having all signals one via instead of some. As it seems that you use vias anyway. The two sided approach allow you to make the lane routing more symmetric at the connectors. Route the pair between the rows of the connector, place the vias that way that you only need to go straight up and down the same distance but also to keep the pair together as long as possible.

Edit: Is the pinning fixed or is the pinning of the connectors your own design? Usually the pair of a signal should be next to each other and not opposite. Because of the problems you're facing: Big differences in length, long not coupled traces.

One problem I have is that I have no control over the pinout, sadly, since I'm connecting to existing devices. These DF56 connectors have staggered pins, so whilst the individual traces from each pair come out from opposite sides of the connector, they are actually next to each other in the cable.

I will try the 50 ohm loosely coupled approach for the top connector and see how that goes.

[dmg]

I assume this is at least a 4 layers board, right?

Thank you for the detailed reply.

This will indeed be a 4 layer board. I actually made a test board for other reasons, but I intentionally paid very little attention to the MIPI routes, pictured below. This was a 2 layer board and the MIPI traces are about 15mm long. This board introduces another cable into the system as well and it all worked fine. Interestingly I was able to add about 20mm of length mismatch (the enamelled wire) to one of the lanes before the data became unreadable.

With regards to the data rate, the clock is at about 700MHz max (4k CSI sensor that I'm switching) so I presume the FSA642 switch is up to the task.

I see what you're saying about using 50 ohm stripline instead of the 100 ohm pair. Do you mean this would be best on the top connector with the large mismatch, or in general for this design?

Would it be better to perhaps bring the traces from the top connector to the other side of the board using vias underneath the connector body, as per the lower connector? This could avoid the dramatic length mismatch between the traces in each pair.


The routing for the third connector is supposed to be on an inner layer, though it would still have uninterrupted ground planes on both sides. I understand the impedance of the trace changes accordingly.

What I mean with the loosely coupled pair has nothing to do with it being a stripline or a microstrip. A differential pair is two normally identical an parallel transmission lines carrying opposite signals. If there were no coupling at all between such transmission lines, the differential impedance of the pair they form would be twice that of a single transmission line. If they're coupled, the more coupled they are the more its differential impedance is reduced. So, a pair composed of two 50 ohm microstrips running parallel but far together from each other would yield a 100 ohm differential impedance, while two 60 ohm microstrips running closer together (tighter coupling) may also yield a 100 ohm differential impedance.

So when you design a differential pair you basically need to choose both the characteristic impedance of the pair and the impedance of the transmission lines that it's made of and adjust the trace separation to yield the desired differential impedance.

For most applications loosely coupled pairs work best, normally starting with the geometry for a 50 to 55 ohm trace to yield a 100 ohm differential pair, but they also occupy more space as both the traces and the separation between them get larger, so sometimes compromises need to be made. The idea is that if you need to uncouple the traces for whatever reason, such as transitioning a connector, going through a via or meandering for lenght matching, loosely coupled traces will suffer less as theyr're mostly uncoupled anyway, so further momentary uncoupling causes less discontinuity than if they were nominally tightly coupled.

So the idea is that you should first calculate the geometry for a single microstrip/stripline transmission line of about 50 to 55 ohm, get the required trace width, input that to the differential pair calculator and adjust the separation until it yields 100 ohm, and then use that geometry.

[IO390]

Thanks for the help everyone. Following this advice I modified the board and it worked perfectly first time.

[DallaThaun]

I know this is an old discussion. But I would really like to ask about this statement you made:

"In your case it would be better to use a large meander rather than several small ones to compensate the length as quickly as possible."

When is it better to do multiple short meander sections vs one larger section?

[toybuilder]

When is it better to do multiple short meander sections vs one larger section?

If you have a curved differential pair, the inside track will be shorter than the outside track as the signal transits the curve.  When it is an S-bend, the left and right turns cancel each other out.  But if you have a U or C-shaped routing, you start to accumulate differences at each corner which you will want to relieve closer to where those difference add up.