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Reduce PWM ripple

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Terry Bites:
Want to reduce PWM ripple? RC LP filters will only get you so far, active filters need opamps. What about this idea... Ripple plus antiripple [attach=1]

ledtester:
Are X1 and X2 standard CMOS inverters -- 74HC04/CD4049?

moffy:
If you use a sample and hold synchronised to the PWM frequency, after filtering, you can almost completely eliminate the ripple.

Cerebus:
There's a full write up of how to do this trick of reducing ripple using what's effectively a differentiator capacitor in "The Art of Electronics The X Chapters". pp 383-385. You can trade off between reduction of ripple and settling time.

I've simulated the AoE scheme (which only uses first order passive filters) in LTSpice with a ±9V, 20kHz PWM square wave settling to a ripple of 22 uV pp (a little over 1 ppm) in 200 ms for a 90% duty cycle and with a worst case ripple 62uV pp (3.5 ppm) with a 50% duty cycle (also 200 ms settling time). Quite impressive. something on the order of 18 ENOB.

T3sl4co1l:
Yes, that's been done:
https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction/
It provides slightly better performance than a 2nd order of similar spec, IIRC?

You can still get faster settling with a higher order active filter, of course; and a 3rd order active only needs one op-amp, which may or may not be preferable to two inverters and one less RC.  YMMV.

Tim

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