Normally, CMC goes on the media side. It's isolated, only the ESD capacitor loading it, two wires, easy job.
There are three cases for PHY side:
1. Push-pull driver, two-line CMC: both pins sink (or not) only, thus there is CM current at this point and wild voltages result. Disallowed!
2. Push-pull driver, three-line CMC: equivalent to the two-line media-side case. Popular for PoE, as choking the power flow (large DC bias) would be onerous.
3. Bridged driver, either CMC: both pins sink and source symmetrically, thus a 2-line is permissible here. (Note that the center tap doesn't need a connection to AVDD; it is usually still bypassed to GND with a small capacitor.)
Bridge drivers are common for GbE+ but sometimes seen on 10/100 PHYs, perhaps compact/integrated ones; signal transmission amplitude is usually reduced as a result (or at least as compared to 10BASE-T definitions), but this is rarely a problem with the sensitivity and compensation used in modern receivers.
If building (2) from discrete components, consider two data-line chokes in parallel (one winding common (CT), remaining windings to TX+,-), as multiline chokes are kind of nonexistent. But, you may have a 3-line available as part of the "chipset"* you're using; the manufacturer may have related/relevant components available.
*In reference to your other thread
https://www.eevblog.com/forum/projects/descrete-transformers-pairs-for-100-mpbs-ethernet/msg5680235/#msg5680235 where you're looking at "chip" style transformers, see what I did there.

Tim