Reliable way to start up latching circuit

[Kryptychon]

Hi,

I'm trying to understand all implications of two different approaches to "start up" a given latch circuit.

Please see the attached schematics titled "Variant A" and "Variant B".

Variant A)
I'm wondering if C1 as a "start up" for this latching circuit will be unreliable. My thought is, that this solution depends on dU/dt beeing "steep" enough to make a current flow through C1, R3 and eventually into the base of Q2 so the latch latches up. Additionally, the current must be at least high enough to overcome U_BE, which in turn depends on R4.

Variant B)
Would increasing C1 and moving it after R5 improve the reliability significantly?
Of course, in this case, the start up behavior is also dependent on dU/dt but is not affected by anything else than the values of R5 and C1.

In any case there is a minimum dU/dt to reliably trigger the latch on power on.

Which of the two variants would you prefer and why?
What else to consider? What am I missing?

Thanks!

Best regards
Kryp

[Doctorandus_P]

I would not call those circuits "latches". They do not latch, they are just switches, which depend on the ^SHDN input. (I assume a uC output).

It is also not clear where the "EN" signal is going to, If that has a too low impedance, then Q2 will never get enough voltage to open the switch.
Also, Q2 may hae some leakage current (depending on temperature, etc) and this may open Q1 a bit. A resistor between base and emitter of Q1 will allow for some leakage current through Q2.

Have a look at the ubiquitous ESR / Transistor tester circuit. It is a design similar to yours, but it has been "well tested", as millions of them have been built.

[Shay]

Second circuit makes more sense logically to me.
As the circuit starts up the capacitor is short circuit. This makes the PNP to saturate instantly. Now when you pull the base of the NPN down, the capacitor has to charge up through the 10k and BE of the PNP. This adds some delay until the circuit is off. However, the discharge of this cap is very quick, so not much delay when changing from OFF to ON.

- however, there is no latching action here. It's more like a normally closed switch.

[Kryptychon]

Hi,

thanks for your answers!

I attached a larger portion of the schematic so it will be apparent where the ^SHDN signal comes from: It's an open collector output of the LM339.

EN is fed into a high impedance input of a gate driver IC.

I guess I fell into the XY problem trap. Sorry for that.

The big picture is: I've a brushed motor controller (H bridge). Temperature and current are compared to adjustable set points. If a set point is reached, the LM339's open collector output pulls ^SHDN to GND.
After such an event, the circuit will stay in the "disabled" state till power cycling or manually resetting it (via SW1), hence I called it "latching circuit" - which may not be 100% technically accurate, I agree.

Regarding the turn off delay, as far as I understand, this simply the time constant given by C1/R5 in the second circuit. Right?
C1 needs to be large enough to allow reliable start up and small enough to not delay turn off unacceptably.

The first attachment is the original circuit, the second one is the circuit incoporating your proposals.