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remove dc offset from signal going into an op amp

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beandigital:
I have a signal that varies between 19V and 17V @ 250kHz. The signal operates in a burst pattern where it outputs 2048 values then stops for a few ms. I want to input this signal into an op amp and remove the dc level. I have a circuit that has a dc blocking capacitor between the signal and the op amp input. The op amp is set as a buffer, and also has a resistor to ground. So I have a high pass filter on the input of the buffer. The issue I have is that I am finding that the circuit takes a long time to settle if I select values that maintain the signal integrity. If I then change the values to speed up the settling time the signal starts to degrade. Are there any other options that will maintain the signal integrity whilst giving a fast settling time? I am open to using a completely different circuit. Thanks

schmitt trigger:
What is the time constant of your R-C coupling circuit?

Could you share some scope images of what you see as signal degradation?

During idle, what is the DC voltage value? Is it steady?


Without knowing the answers to the above questions, and with many actual details missing, my first idea would be to have a circuit which would get the average DC voltage integrated for a long time, and apply that voltage to a difference amp which also processes your signal.

ejeffrey:
This probably means that your pulse sequences are not DC balanced, or have substantial signal content below the cutoff of your highpass filter.  This causes the capacitor in your RC to charge up and then bleed off slowly.

Is the output during the "idle" periods the DC offset?  If so you can use a sample-and-hold architecture to sample the DC offset only during the idle periods.  Then use an op-amp difference circuit to subtract that from the input signal.

Marco:
How long does it send and how long does it not?  Unless it's not sending for say 10× .more than it is, a capacitor is not the right solution.

The signal presumably has DC even after you remove 18v. So if the steady state of the signal is 17v, it will always try to pull the signal up during the burst.

strawberry:
offset OP reference input 0V to 17V and amplifie difference

capacitor give error due to PWM average value

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