Signal generator board
(https://live.staticflickr.com/65535/54126645282_7a6d842bea_c.jpg) (https://flic.kr/p/2qsZcU7)
[attachimg=1]
DACs & purpose
The most obvious feature of this board is all the large CPLDs. However, I'm calling it the "signal generator board" because of the 5x (!!) DAC channels in the analog/mixed-signal section down the left-hand side. To sum up:
- 200 ksps
- 2.5 Msps
- 2.5 Msps
- 10 Msps
- 10 Msps
So we have one slow channel, two moderately fast channels, and two fast channels. The op-amps nearby probably are for filtering & scaling/offsetting the DAC outputs appropriately - the slow DAC might even provide a programmable DC offset for some of the other analog output channels. The voltage references (2x 10V, 2.5V, and 5V) probably feed the DACs and/or create precision offsets for the op-amps to use.
The form factor and connector at the bottom look similar to the previous "analog input" board, so it could be from the same system. I can't think of any video or imaging applications which would need single-digit-Mhz signal generation, so my best guess is that this is doing DDS (https://en.wikipedia.org/wiki/Direct_digital_synthesis) generation of radar transmit pulses. There's all sorts of ways to modulate a radar transmit pulse (https://www.radartutorial.eu/08.transmitters/Intrapulse%20Modulation.en.html) to improve its performance (https://www.radartutorial.eu/02.basics/Stepped%20Chirp%20Radar.en.html), and so generating an arbitrary transmit waveform in a programmable way would be extremely useful. The multiple output channels might be up-converted to different transmit frequencies as part of a frequency-diversity radar system (https://www.radartutorial.eu/01.basics/Frequency%20Diversity%20Radar.en.html), or maybe fed to separate antennas for some very basic phased-array beam steering (https://www.radartutorial.eu/06.antennas/Digital%20Beamforming.en.html).
Programmable logic
Whatever the DACs' output signals do, there's a good chance their input data is fed directly from the various programmable logic on the board, both the Altera (now Intel) MAX 7000 series (https://cdrdv2-public.intel.com/654718/m7000.pdf) electrically-erasable CPLDs (https://en.wikipedia.org/wiki/Programmable_logic_device#CPLDs) in the larger black-lid packages...
(https://live.staticflickr.com/65535/54127770603_e83abbf353.jpg) (https://flic.kr/p/2qt5Yqc)
...and the MAX 5000 series (https://cdrdv2-public.intel.com/654619/m5000.pdf) UV-erasable CPLDs closer to the connector.
(https://live.staticflickr.com/65535/54127940400_9c89d1f7ce.jpg) (https://flic.kr/p/2qt6QTJ)
If you zoom into the image, you can see the two columns of 4 Logic Array Blocks, one at the left and one at the right, plus the global routing/clocking in the middle column.
Each of these CPLDs has 100-200 macrocells, and each macrocell consists of one register fed by the programmable input logic terms - so there's not enough programmable logic on this board to implement a soft processor, for example, but it can still do a good deal of computation & sequencing. 192 flip-flop is enough for 12x 16-bit registers, for example.
[attachimg=2]
Waveform RAM
There's also a lot of RAM on this board: the 3x SMJ55161 SRAM chips here hold 768K 16-bit words total, so this probably holds waveform data for the DACs. If you check out the datasheet (https://www.alldatasheet.com/datasheet-pdf/view/181568/TI/SMJ55161.html), the SMJ55161 has an interesting architecture. There's a random-access port (good for writing waveform data, in this case) and a separate serial-access port ("SAM") meant for FIFO-like continuous reads. The SAM is specifically meant to feed a continuous stream of data to DACs for use in computer video cards; the datasheet advertises "Up to 45-MHz Uninterrupted Serial-Data Streams", and mentions...
...a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port)
that enables real-time-register-load implementation for continuous serial-data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array.
This seems ideally suited for feeding a continuous stream of waveform data to the DACs, or possibly to the CPLDs first for some on-the-fly scaling or other basic math.
(https://live.staticflickr.com/65535/54127940440_1ec9a4d453.jpg) (https://flic.kr/p/2qt6QUq)
CPU
There's also a 68HC11 processor in the corner with its own RAM & program memory nearby:
(https://live.staticflickr.com/65535/54127940385_94ce962417.jpg) (https://flic.kr/p/2qt6QTt)
This probably does the high-level control and sequencing, and may do the math (with the help of some of the programmable logic?) to generate the waveform data and store it in the waveform RAM we just discussed.
FIFOs & interface
A couple FIFOs (1K x 9 bits each) live next to the backplane connector:
(https://live.staticflickr.com/65535/54127485046_6953ebf83e.jpg) (https://flic.kr/p/2qt4vwN)
These are likely responsible for moving data into this board from elsewhere in the system. It's possible that the 68HC11 doesn't do any of the waveform-generation math, and instead, a different board generates the waveform data and loads it into the waveform RAM here via these FIFOs and the UV-erasable CPLDs.
You can also see a row of buffers in that photo, for digital signalling to and from the backplane connector.
Analog
The analog mux and quad comparator at the bottom-left corner may be used together, for monitoring a variety of different DC inputs for any out-of-range conditions.
(https://live.staticflickr.com/65535/54127483826_a9e93d2957.jpg) (https://flic.kr/p/2qt4vaL)
Sadly, I can't trace the circuitry in the analog & mixed-signal section: unlike with the analog input board, all the traces are run on an inner layer that's hidden by a copper plane, so I don't have a good way of seeing what's connected without spending a year doing continuity checks through the conformal coating, or getting an X-ray.
(https://live.staticflickr.com/65535/54127939485_62028335b6.jpg) (https://flic.kr/p/2qt6QBX)
(https://live.staticflickr.com/65535/54127483296_2849785f13.jpg) (https://flic.kr/p/2qt4v1C)
Resistor arrays
I was curious what some mystery packages were (marked as "??" in the annotated board view at the beginning), which consistently turned up near the line drivers, so I popped the lid on one:
(https://live.staticflickr.com/65535/54127829194_c1bc6e5844.jpg) (https://flic.kr/p/2qt6gQo)
(https://live.staticflickr.com/65535/54127948053_4342b6b86c.jpg) (https://flic.kr/p/2qt6TaF)
Turns out it's a resistor array, with 19 separate resistors bussed to a common terminal.
Mechanical
Also, this board, like the last one, has a thick aluminum stiffener with cutouts for all the through-hole pins and a few SMT components on the back side (especially power-filtering caps for the CPLDs).
(https://live.staticflickr.com/65535/54127827899_7aa7d57b10.jpg) (https://flic.kr/p/2qt6gs4)
(https://live.staticflickr.com/65535/54127768753_ff5dd963fc.jpg) (https://flic.kr/p/2qt5XSi)
Here's a couple final glamour shots of the board:
(https://live.staticflickr.com/65535/54127829779_aff81d0bf6_z.jpg) (https://flic.kr/p/2qt6h1t)
(https://live.staticflickr.com/65535/54127770578_008762d6b7_z.jpg) (https://flic.kr/p/2qt5YpL)