Routing Crystal

[girishv]

Hi,

I am designing a board using STM32 G0. I am using a 16MHz crystal. I want to make sure I am laying out and routing the crystal and decoupling capacitors correctly. Here is the screenshot of the crystal and decoupling portion of layout.

Do I need to make any changes?

[Faranight]

At a quick glance I have some comments...
The clearance between GND pads and the GND fill seems a bit large compared to other pads. Can you reduce it?
I would also use some vias close to the GND pads of the IC (and crystal) to connect the top ground plane to the bottom one (assuming your board is not top-layer only).
The caps seem close enough to the crystal, but personally I would put the crystal closer to the uC.
Also, the decoupling cap of the uC needs close connections to the uC pads. While your 3V3 pad does gave a close connection to the cap, the GND pad does not - it goes waaaaay around (edit: and has no connection to the main GND plane). This is very bad practice.

[srb1954]

At a quick glance I have some comments...
The clearance between GND pads and the GND fill seems a bit large compared to other pads. Can you reduce it?
I would also use some vias close to the GND pads of the IC (and crystal) to connect the top ground plane to the bottom one (assuming your board is not top-layer only).
The caps seem close enough to the crystal, but personally I would put the crystal closer to the uC.
Also, the decoupling cap of the uC needs close connections to the uC pads. While your 3V3 pad does gave a close connection to the cap, the GND pad does not - it goes waaaaay around (edit: and has no connection to the main GND plane). This is very bad practice.

The GND for the 3V3 decoupling cap appears to rely on the connection being jumpered  between the two ground pins on the crystal - not a good idea as it considerably increases the parasitic inductance on the GND path and potentially couples any GND noise into the crystal circuit.

[pgo]

General comments:

- The ratsnest shows that the ground connections are not complete yet.  I presume you are adding vias to a ground plane.

- The purpose of the cap on Vcc is to bypass the power on the cpu.  There should be very short path between pins 8 & 9 and this capacitor. (assuming 8/9 are power supply connections)  As shown the path on Gnd is indirect. Move some traces so there is a direct connection.

-  The extra space around the ground pads on the SMTs are for thermal relief and should probably be kept (esp. if hand soldering).

- Try to keep the ground beneath the Xtal intact on the reverse of the board. No other conductors running there if possible.

- Move the crystal closer and shorten the traces in general.

[girishv]

I have changed the layout based on feedback and suggestions from @Faranight, @srb1954 and @pgo.

Here is the revised layout with routing.

Edit: Uploaded the correct screenshot.

[Faranight]

The extra space around the ground pads on the SMTs are for thermal relief and should probably be kept (esp. if hand soldering).

Hmm, I use the same copper clearance for thermal relief on the GND pads and all other netlist traces, and I've never had any problems hand-soldering SMD components.
Though I've had some trouble doing certain THT components on multi-layered PCB's where the hole was in contact with several layers of ground fill. That's where I tend to use bigger relief.

I have changed the layout based on feedback and suggestions from @Faranight, @srb1954 and @pgo

Dude, what are you even doing here? You have terminated the power connection to the uC. The C7 capacitor is now just standing still - it has no connection to the microcontroller whatsoever. Please route the C7 first. Connect it to pin 8 and 9 of the uC with very short traces. Also, you don't need to route extra traces between pads and GND vias, just let the zone copper fill do the job. The pad 2 of C10 is floating. Uggghhh.

[girishv]

I have changed the layout based on feedback and suggestions from @Faranight, @srb1954 and @pgo

Dude, what are you even doing here? You have terminated the power connection to the uC. The C7 capacitor is now just standing still - it has no connection to the microcontroller whatsoever. Please route the C7 first. Connect it to pin 8 and 9 of the uC with very short traces. Also, you don't need to route extra traces between pads and GND vias, just let the zone copper fill do the job. The pad 2 of C10 is floating. Uggghhh.
[/quote]

Sorry for testing your patience. I have routed the C7 and C10 correctly. I have removed the traces between pads and GND vias.

The distance between the capacitor pad and MCU is about 1mm. Should I bring them closer?

Further, the ground pour settings are

Clearance: 0.15mm
Minimum Width: 0.3mm
Thermal relief gap: 0.5mm
Thermal spoke width: 0.5mm

Any suggestions?

Meanwhile, here is the revised layout.

[Faranight]

I have some questions for you.

- How many layers does this board of yours have? One, two, four? Ideally you'd want at least two layers, having the bottom one act as the main GND plane. For four layers there are different arrangements, but I take it you're not that far yet since you're struggling with some basic layout issues, so I'm gonna leave that topic alone for now.

- How are you going to have this board made? Are you going to etch it yourself or are you going to have a fabhouse (i.e. JLCPCB) do it for you?

- What kind of soldering tools do you have access to? Simple soldering iron? Soldering station? Hot air station? Reflow oven??? Depending on what you have access to, you might want to design the board accordingly. you may not need to use such aggressive thermal reliefs at all. For example, the SMD crystals might be difficult to solder by hand with an iron alone, but a hot-air station works wonders here. I use it most of the time to solder crystals, and for some SMD components I don't use any thermal reliefs at all.


For the decoupling cap C7 you're still using a GND connection longer than I'd be comfortable with - it goes way around through the GND vias. You ideally want as short connections as possible to the uC. Please see the attached pic.

[girishv]

I have some questions for you.

- How many layers does this board of yours have? One, two, four? Ideally you'd want at least two layers, having the bottom one act as the main GND plane. For four layers there are different arrangements, but I take it you're not that far yet since you're struggling with some basic layout issues, so I'm gonna leave that topic alone for now.

This is a 2 layer board and bottom layer is GND plane.

- How are you going to have this board made? Are you going to etch it yourself or are you going to have a fabhouse (i.e. JLCPCB) do it for you?

- What kind of soldering tools do you have access to? Simple soldering iron? Soldering station? Hot air station? Reflow oven??? Depending on what you have access to, you might want to design the board accordingly. you may not need to use such aggressive thermal reliefs at all. For example, the SMD crystals might be difficult to solder by hand with an iron alone, but a hot-air station works wonders here. I use it most of the time to solder crystals, and for some SMD components I don't use any thermal reliefs at all.

I am going to use a pcb fabrication house. I am considering a local company to save time. The local company has limited capabilities.

I do have a good soldering station and hot air. I am considering building DIY reflow oven.

Meanwhile, I have updated the layout based.

[Kleinstein]

The µC GND pins still needs a connection to GND.

For the crystal is depends on how critical the clock is. As shown it may work ok for a more general use (e.g. need a clock for a UART or similar), but it would not be a low noise / stable clock for a frequency counter or similar. For a critical clock I would prefer a separate clock generator chips instead of the µC internal oscillator with a bare external cystal anyway.
As shown, current in the ground plane near the crystal can effect the clock stability. Ideally the 2 capacitors at the crystal would have there own linkt to the µC GND, not via the general ground plane.

[girishv]

The µC GND pins still needs a connection to GND.

For the crystal is depends on how critical the clock is. As shown it may work ok for a more general use (e.g. need a clock for a UART or similar), but it would not be a low noise / stable clock for a frequency counter or similar. For a critical clock I would prefer a separate clock generator chips instead of the µC internal oscillator with a bare external cystal anyway.
As shown, current in the ground plane near the crystal can effect the clock stability. Ideally the 2 capacitors at the crystal would have there own linkt to the µC GND, not via the general ground plane.

I have revised the layout  and µC GND pin is connected to ground using a via. I need to read more on crystal placement and explore separate clock generator.

Meanwhile, I have updated the layout.

[Faranight]

Do you have anything against placing the ground vias directly on the GND pads of the SMD components? I know some fabhouses don't support it or maybe there's trouble with SMD reflow soldering because open vias will suck in solder paste. But, if you're doing soldering by hand, then there shouldn't be any major issues.

You could also consider placing some SMD components on the bottom side of the board. I usually put decoupling caps right underneath the power pins of a microcontroller, if I'm tight on board space. And both pads are connected directly by a few tiny vias that fit on the uC pad. Fabhouses usually have size limitations i.e. minimum supported drill hole diameter - see the fabhouse capabilities. Normally, they would offer a document with all details and tolerances described.

Since you have a double-sided board, you could try to route some short traces on the bottom side, if you're tight on space. Ideally, you'd choose slow switching signals like LED's. Faster lanes like SPI, I²C and the crystal clock should ideally be on the same side as the uC. If not, at least put a GND via (top GND plane to bottom GND plane connection) directly adjacent to the VIA where the signal trace penetrates the PCB to another layer. But then again, I'm already getting ahead of myself here and going into advanced/high-speed PCB routing.

-Far.

[girishv]

I am very grateful for all the advice and feedback received. I have learnt a lot in past few days.

I did changed the size of decoupling capacitors from 0603 to 0402.

Here is the revised layout. I have routed only critical components in the attached screen grab.



Please review.

[PCB.Wiz]

I did changed the size of decoupling capacitors from 0603 to 0402.
Here is the revised layout. I have routed only critical components in the attached screen grab.

Use whatever caps you can assemble easily. I find 0402 slower to manage than 0603 which are slower than 0805, but sometimes smaller caps allow a better layout.

If you are worried about emissions, the 'ideal' crystal layout is one where the two crystal caps go directly to the MCU ground pin, and share no other paths.
Ground guard bands around the xtal nodes are also good practice.
In your case, that would need a track under a cap, which may not fit with those sized caps ?

[2nOrderEDO]

I suggest you take a good look at application note AN2867 from ST: "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs", sections 7.1 and 7.2. There are some nice layout examples.

I have followed those guidelines with good results. As a general rule, try to put all the components as close as possible and minimize all the lengths.

Here is a reference design for a RTC clock from my own collection:

Notes for your special case:

• Based on the courtyards I see in your screenshots, there is still plenty of distance between the components. Try placing the crystal as close as possible to the MCU to try to minimize the length of the crystal pin nets, and put the rest of the components also as close as possible to the crystal.
• You included the serial resistor for the drive strength. That is good, just try to make everything as compact as possible. The example I'm sharing does not have that resistor, so layout is a little bit easier and more compact
• With a two layer board it is not possible to make the ground split in my example, just keep a solid ground plane and it should be good. The break in the plane is not really needed as long as you make sure any return paths from the HS signals do not cross the crystal area.
• For LQFP packages, the nearest ground MCU pin to connect the local clock plane and the shielding tracks could be a little bit far away, which is kind on annoying.

I hope this information proves useful and wish you the best of luck with your oscillator design project.