Author Topic: AES3/EBU input design - can you help please?  (Read 3995 times)

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Offline YansiTopic starter

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AES3/EBU input design - can you help please?
« on: May 25, 2016, 07:20:28 pm »
Hi!

I am currently working on a project, which should have an AES3 input (the professional balanced version of SPDIF). But  I haven't found much info about how to design a proper transformer isolated input and the differential receiver.

The requirements are: support both 48 and 96kHz audio stream, that is up to 12mbps data. (SPDIF bit rate is 128*fs)

I have tried my best to find a suitable transformer, which would not cost a fortune and would be easily available. Meh.. I couldn't find almost any, which would be rated at the double sampling 96kHz (12Mbaud).
The only one available I have found is Pulse PE-65612 (PE-65812 respectively). But it is rated only up to 7Mbaud with 25ns risetime (not good enough I think). God knows if it will run at the double sampling rate, at 12Mbaud. It is almost twice its rating. The datasheet is attached. What transformer would you suggest to use?

It is quite difficult to find one with high primary inductance (1mH+). Those ethernet transformers, which are quite cheap and fast enough have mostly only 300uH primary inductance and I quite unsure how those will handle the AES3 voltage levels at lower samplerates (i.e 6Mbaud only at 48kHz). I don't think it is a good idea to use one of these either. Dead end. What transformer should I use? What do you recommend?

The differential receiver. I have read several times on several places, that RS422/485 line receivers may be used for the AES3. But the old good SN75176B is only up to 10Mbaud. Too slow. And I couldn't find a better one. Some parts from LTC popped up, but those were mostly 0pcs in stock or expensive as hell. Do you have any experience or can you suggest a cheap differential line receiver usable together with the AES3 bus? I need a CMOS 3.3V level on the output.

The circuit I could come up with is this one attached.  R36-37-38 is an optional voltage divider (let's say its sole purpose is for experimenting with transformers), should be omitted. R39 is the termination resistor. The AES3 line should have 110ohm impedance (the transformer is 1:1 ratio). R40-C70 is a kind of impedance correction/equalization circuit I have seen somewhere used, but couldn't figure out how did they obtained the correct values. The R was some hundred ohms and the cap some puff. Is this circuit a correct approach?

How should I interface the secondary side of the transformer to the line receiver (like 75176)? Probably have to be biased, not left floating. Maybe divide the termination resistor in half, couple the center to ground with a 100n cap and bias it with half the receivers input range/supply.

Thank you for suggestions, this is my first SPDIF/AES encounter.  :)
Yan

 

Offline ConKbot

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Re: AES3/EBU input design - can you help please?
« Reply #1 on: May 25, 2016, 07:53:18 pm »
In some of my looking, magnetics seem to be better found by going to the manufacturer's websites than digikey/mouser. Have you checked out murata power? http://www.murata-ps.com/en/products/magnetics/pulse-transformers.html they have some chunky wideband transformers with a few mh of inductance and plenty of V-us time constant.

I haven't used pulse transformers for communications, but I'm assuming you can calculate the rise time from the leakage inductance, secondary dcr, winding capacitance and load capacitance?
« Last Edit: May 26, 2016, 01:50:23 am by ConKbot »
 

Offline Mark Hennessy

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Re: AES3/EBU input design - can you help please?
« Reply #2 on: May 25, 2016, 08:17:19 pm »
AES3 is my bread and butter, and I know it well. I've never had to specify a transformer though. But all the ones I see are cheap pulse transformers - nothing special needed. Some older gear uses hand-wound transformers using small ferrite toroidal cores...

Think about the signal: it is bi-phase mark coded, and for 48KHz sampling, the majority of the energy is concentrated at 1.5MHz and 3Mhz. There is some at 1Mhz (X preambles). For 96k, it's obviously double those numbers - but I'll default to 48kHz because I know most of the numbers off the top of my head. This is not difficult as such, but obviously, these are square waves that need to have their rising/falling edges preserved to minimise Fs jitter. The interconnecting cable will be the main source of HF loss.

In terms of timing, a logic "1" in the source data gets coded up as a single cycle of a 3.072MHz square wave that has a period of 325ns, so that puts your 25ns transformer into some sort of perspective. The datasheet you attach shows a -3dB bandwidth of 100kHz to 55MHz, which seems pretty good to me.

Inherently, bi-phase coding has no DC offset and is polarity agnostic. It seems to be the norm to float the transformers rather than bias them. Capacitive coupling at each end is part of the standard - I don't see that on your schematic. Optional HF EQ can be added to the receiver for long cable runs.

Also, it is actually recommended to limit the slew rate (for EMI reasons) - the minimum rise time should be no less than 5ns, but can be as high as 30ns (at the source end, correctly terminated).

RS422 transceiver chips are the norm for this IME. I can pull some cards and look up part numbers when I'm back at work tomorrow.

I'm not sure where you get your baud rate figures from though - I suspect you've confused a sentence from the standard ("The upper frequency is 128 times the maximum frame rate") which relates to frequency content on the interface, not data rate. At 48kHz, 2 times 32 bits of source data is sent per sample period (20.8us), so that's 3.072Mb/s. When coded with bi-phase mark coding, the notional "speed" depends on the actual data, so I'm not sure it's as simple as you think? As indicated earlier, 3.072MHz is the highest frequency square wave you'll see (double for 96kHz). 128 times 48kHz is 6.144MHz, so that's the minimum suggested BW needed to get a passable square(ish!) wave out the far end.

The voltage is very loosely specified - from memory, it's 2 to 7V pk-pk at the source when correctly terminated. The threshold of the receivers should be 200mV pk-pk. In practice, with long cables it's HF loss rather than voltage loss that stops it working - and the first bit to go is the 7th bit in the X preamble. At work we demonstrate this with different lengths of cable that we cascade together, and use a passive (BBC designed) breakout box to interface the AES interface to a 'scope. Works well...

Although the voltages can be quite high, the fact there is virtually no energy below 1MHz offsets that.

When understanding AES3, I find it much easier to consider the coded signal in analogue terms - after all, this is an analogue electronics problem.

As I say, I can have a look at some typical gear when I'm back at work tomorrow.

Hope that helps,

Mark
 

Offline linux-works

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Re: AES3/EBU input design - can you help please?
« Reply #3 on: May 25, 2016, 08:29:13 pm »
plug for a friend's website: www.amb.org - look for y3 or gamma3 dac.  you can find lots of info about spdif trafos including some pretty 'good' ones.

plug for another friend, jon, at http://www.scientificonversion.com/ (jon knows aes and spdif quite well and builds/sells high spec trafos for digital audio).

HTH

Offline YansiTopic starter

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Re: AES3/EBU input design - can you help please?
« Reply #4 on: May 25, 2016, 09:14:49 pm »
Thank you Mark for your detailed reply!

Sure, i have forgot to place there a DC blocking cap on the input.  1uF ceramic should be enough I think.

Yes, I might confused the actual "content" frequency on the bus with the clock needed to produce the biphase stream. (I am still kind of with my mind switched to the digital domain implementation)  :) So then the transformer I have chosen might be sufficient. it is cheap, has fully available datasheet and the Pulse company is quite well known for me. (I have used their ethernet trafos in the past).

Can you please get me the part number of the 422 receiver chip? The classic 75176B should work up to 10megbits. At 96kHz the SPDIF should produce a maximum frequency 6MHz, but the equivalent bit rate for the receiver is therefore 12M. Which is kind of out of the border. I am looking forward for your suggestion, for the receiver part number, many thanks! 

Also may I ask, what is the best practice to do with the ground wire from the AES3 cable? The data pair is isolated with a transformer, so it is kind of strange to connect the cable ground directly to my local ground (might introduce ground loops and hum into my analog ground). How is it usually done? 


Yeah, I have found the ScientificConversion company. But it looks kind of iffy.  Doesn't leave much confidence. And I haven't seen their parts anywhere to buy either. I have also dug through the Murata parts, but they are mostly unavailable or quite pricey in single quantities or full specification wasn't anywhere to be found for some types. So the Pulse PE-65612 was a clear winner. Hope this one will work with the 96kHz audio data.

Note: I am not building any audiophile DAC and I will not even try to mimic that kind of stuff. I am just trying to build a custom piece of kit for speaker system signal processing. But trying for some reasonable spec though (PCM4104 + PCM4202 and a load of OPA1632s)  ;)
 

Offline linux-works

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Re: AES3/EBU input design - can you help please?
« Reply #5 on: May 25, 2016, 09:26:47 pm »
scientific conversion is the real deal.  jon knows his stuff.  its not cheap but these trafos are engineered and not just thrown together.  I know jon is working on higher speed stuff for studio standards.  he's known in the industry and had been around quite a while.

if you need stuff that runs at high spdif data rates, your choices are not so numerous.  lots at 44/48k but the old pulse trafos are not really rated beyond that (I have used them, and even toslink at 96k but its not really per the spec).


Offline YansiTopic starter

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Re: AES3/EBU input design - can you help please?
« Reply #6 on: May 30, 2016, 02:40:36 pm »
Mark Hennessy:  Have you looked for the differential line receiver part numbers?

Is SN75176 (as a receiver) suitable for SPDIF? Both at 48kHz/96kHz?  Seems it's only good enough for 48k (6mbits), the 96k (12mbit) is a bit out of its spec. Unfortunately finding a higher speed receiver for 422/485 is not easy. There are loads of f*cking expensive parts from LTC which are nowhere in stock and then some (also quite expensive) ones from Maxim or Intersil:

These two I consider to use, if the 75176 can't keep up with the 96k stream:

ISL3179: http://www.intersil.com/content/dam/Intersil/documents/isl3/isl3179e-80e.pdf
MAX3280: http://datasheets.maximintegrated.com/en/ds/MAX3280E-MAX3284E.pdf

The second one is quite cheap (about ~1$) and fast enough, but I don't like it's package, will be a pain in the ass to find a replacement, if that would be necessary. But I will probably use this one.

And also what about the ground pin from the AES input? What to do with it? Tie to local ground? (then the galvanic isolation makes no sense) Float? Couple to local ground through RC?

Thank you
 

Offline Mark Hennessy

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Re: AES3/EBU input design - can you help please?
« Reply #7 on: May 30, 2016, 10:23:43 pm »
Mark Hennessy:  Have you looked for the differential line receiver part numbers?

Apologies - Friday was busier than expected, so I didn't get the chance to look. Back next week...


And also what about the ground pin from the AES input? What to do with it? Tie to local ground? (then the galvanic isolation makes no sense) Float? Couple to local ground through RC?

Pin 1 is generally connected to ground IME.

The transformers are more about optimum balanced operation (hence noise rejection, etc) than galvanic isolation as such.
 


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