Start by carefully working out what the the important figures are that you actually need to achieve. With a UART, what you need to do is ensure your clock is accurate enough so you're sampling at some valid point within each data bit.
You don't need to sample each bit many times, and you don't need to sample each bit exactly in the middle. Just ensure that, assuming you synchronise the sample point at the beginning of the start bit, you're still sampling at some point within the valid window by the time of the stop bit.
If you work out the worst case clock slip, I suspect you'll find that you don't need 1% accuracy. You can slip nearly half a bit in 10 bits.
If it helps, use one of the PLLs in the FPGA to generate some other, more convenient reference clock from the 150 MHz input. You should be able, for example, to get 80 MHz from 150 Mhz using a PLL, and then oversample the incoming data 8 times.