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Saturating a MOSFET with a constant current sink driver
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Wimberleytech:

--- Quote from: Oleenick on January 07, 2020, 10:07:36 pm ---
So apart from my irresponsible description of voltage (thanks I'll make sure to correct it in future), its just that I assumed that source will be at 5V after saturing the MOSFET given the load. In a previous case, does that mean if the MOSFET was on and 10A of current started flowing from drain to source, the voltage across drain and source would be ~3V?

Thank you for continuing to help.

--- End quote ---

Didn't mean to be pejorative.
Think about this.  Imagine an NPN BJT with the collector at 5 volts and the base at 5 volts.  With some amount of current flowing collector to emitter, will the emitter voltage ever be five volts?  MOSFETS are a different beast, but similar in this way. 
If the gate and drain of an NMOS transistor are connected to five volts, the source can never rise above 5V-Vth. 

If you know how to use LTSpice, I will generate a simulation for you to examine
Oleenick:

--- Quote from: Wimberleytech on January 07, 2020, 10:32:19 pm ---
--- Quote from: Oleenick on January 07, 2020, 10:07:36 pm ---
So apart from my irresponsible description of voltage (thanks I'll make sure to correct it in future), its just that I assumed that source will be at 5V after saturing the MOSFET given the load. In a previous case, does that mean if the MOSFET was on and 10A of current started flowing from drain to source, the voltage across drain and source would be ~3V?

Thank you for continuing to help.

--- End quote ---

Didn't mean to be pejorative.

--- End quote ---

No no its fine I didn't take it that way. I'm glad you corrected me.


--- Quote from: Wimberleytech on January 07, 2020, 10:32:19 pm ---Think about this.  Imagine an NPN BJT with the collector at 5 volts and the base at 5 volts.  With some amount of current flowing collector to emitter, will the emitter voltage ever be five volts?  MOSFETS are a different beast, but similar in this way. 

--- End quote ---

The emitter voltage would depend on the current flowing collector to emitter. So the voltage across base and emitter would be influenced by the current flowing collector to emitter, which is governed by the transistors RDSon. I think?


--- Quote from: Wimberleytech on January 07, 2020, 10:32:19 pm ---If the gate and drain of an NMOS transistor are connected to five volts, the source can never rise above 5V-Vth. 

If you know how to use LTSpice, I will generate a simulation for you to examine

--- End quote ---

I do know the basics of LTSpice, but I just "simulated" it on a breadboard with a PMOS and NMOS.

Measuring voltage across source and ground (the load should be at 5V).
NMOS (load is not at 5V):


PMOS (load is 5V):

Wimberleytech:
Please draw what you are measuring...like what I show here.
Oleenick:

--- Quote from: Wimberleytech on January 08, 2020, 02:51:19 pm ---Please draw what you are measuring...like what I show here.

--- End quote ---

Here are the two circuits I was testing, minus the capacitor which I didn't add to the breadboard.
My voltage measurements were across the blue and red nodes on each NCH and PCH diagram.
Oleenick:
I think I've finally found a nice MOSFET. If you're curious (https://au.element14.com/infineon/ipb120p04p4l03atma1/mosfet-p-ch-40v-120a-to-263-3/dp/2480803)

I've been looking more into MOSFETs, and I can see clearer now what's been described to me here.

Thanks for all the support.
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