So apart from my irresponsible description of voltage (thanks I'll make sure to correct it in future), its just that I assumed that source will be at 5V after saturing the MOSFET given the load. In a previous case, does that mean if the MOSFET was on and 10A of current started flowing from drain to source, the voltage across drain and source would be ~3V?
Thank you for continuing to help.
Didn't mean to be pejorative.
No no its fine I didn't take it that way. I'm glad you corrected me.
Think about this. Imagine an NPN BJT with the collector at 5 volts and the base at 5 volts. With some amount of current flowing collector to emitter, will the emitter voltage ever be five volts? MOSFETS are a different beast, but similar in this way.
The emitter voltage would depend on the current flowing collector to emitter. So the voltage across base and emitter would be influenced by the current flowing collector to emitter, which is governed by the transistors RDSon. I think?
If the gate and drain of an NMOS transistor are connected to five volts, the source can never rise above 5V-Vth.
If you know how to use LTSpice, I will generate a simulation for you to examine
I do know the basics of LTSpice, but I just "simulated" it on a breadboard with a PMOS and NMOS.
Measuring voltage across source and ground (the load should be at 5V).
NMOS (load is not at 5V):

PMOS (load is 5V):
