At the moment the top pin the the drain and the bottom is the source on the MOSFET in that diagram. When it is saturated I intend for the LVL0 net to be placed at a +5V potential. I think I see what you mean, that the drain pin should be where the current is "drawn" from through source. But then that diode on the diagram shows that current flows from drain to source, or am I wrong assuming that? Could you elaborate on this to help me out of my confusion.
First, see mikerj's comment.
I will elaborate.
A MOSFET is fundamentally a four-terminal device: Drain, Source, Gate, Body.
The Body terminal is also called: substrate, bulk, well, tub(rare...but I can think of one company that used this term).
A MOSFET is a "majority carrier" device. For an nch MOSFET, the majority carriers are electrons, for pch, they are holes.
In order for current to flow from source to drain (or drain to source), a channel must be created...a path for majority carrier current to flow.
For a pch device, the Body (substrate) is lightly-doped n-type silicon and the drain/source are heavily-doped p-type silicon.
In order to create a channel, the lightly-doped substrate must be "inverted" (in simple terms, converted to p-type) so that majority carriers (holes) can flow.
An appropriate potential "relative to the substrate" must be applied to the gate in order to form the inversion layer. For a pch MOSFET, this voltage is negative with respect to the substrate terminal. Therefore, the gate voltage must be lower in potential than the substrate terminal. Moreover, you must also consider the potential of the drain/source terminals. At the device level for conventional MOSFETS (no DMOS or asymetric MOSFETS), there is no physical distinction between drain and source. They are interchangeable. But, in order for the first carrier (electron or hole) to leave the source terminal, the region at the edge of the source must be inverted. Thus, for a pch device, the source must be at a higher potential than the gate. Either physical drain/source terminal can serve as the source depending solely on terminal conditions (voltage relative to the other terminals).
OK this may be a lot to absorb. Here is a simple rule for a four-terminal pch MOSFET.
1) the substrate voltage must be equal or greater than the other to conducting terminals (not the gate terminal)
2) the source terminal is the terminal with the highest voltage of the two conducting terminals
3) the drain terminal is the terminal with the lowest voltage of the two conducting terminals.
In the case of the transistor you used, the substrate is tied internally to one of the other terminals. By applying the rule above, you will see that the terminal attached to the substrate must be the source terminal.