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Searching a high-side driver ic for a p-channel MOSFET, do you know any?
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Ian.M:
Please note edit to reply #29

All component references in this post refer to the schematic from reply #32, not those from my sim.

It looks basically sane, but I'd tighten up the layout as much as possible to reduce trace lengths and thus stray capacitance and loop area.    I'd also beef up the collector and emitter traces to Q3,Q4 (and out to the gate) even to the point of having to neck them down to transition to the pad.   It would also be beneficial to reduce the length of the gate trace to the MOSFET.   I'd also put a footprint for an optional series gate resistor or ferrite bead in case the MOSFET breaks into HF oscillation while sweeping through its linear region on each transition.  Bridge it with a trace you can cut, or populate with a zero ohm jumper.

Also the large hole in the ground plane is problematic, and likely to seriously increase its radiated emissions.  Maybe re-do with most of the MOSFET driver circuit traces on the other side, but be careful to avoid long slots in the ground plane.  More vias are definitely preferable to long slots.   The only place you may *WANT* a hole in the ground plane is under the node driving the bases of Q1,Q2, where stray capacitance is very detrimental to the rise and fall time.

On the subject of decoupling.  Its somewhat of a black art* unless you can consider the effects of all the parasitics involved (both internal to the caps and trace inductance and resistance) in detail.  Unfortunately I don't have a good reference for a tutorial that will get you up to speed with high current HF and pulse circuit decoupling as I learnt what little I know of the art# well before internet tutorials.   Minimising loop area is key to keeping trace inductance under control.   

Its desirable for all the gate charge required to switch the MOSFET to come from the nearest decoupling capacitors to the emitter of Q4 without significant voltage shift at the emitter.   If the capacitance was numerically equal to the total gate charge, with no other decoupling, you'd get a 1V + I*ESR voltage shift at the emitter.  You probably want far less than that, so try an order of magnitude more capacitance.  You may have to split it into multiple capacitors to reduce ESL.   Minimise track length to the decoupling and if on the opposite side to the ground plane, use two vias for each decoupling cap ground pad to reduce the effect of the via inductance.

* far less so nowadays, as simming the parasitics involved can be done in a few minutes in a SPICE program  on your desktop without deep knowledge of mathematical programming rather than having to write a Fortran program to model the network and submit it as a batch job to a mainframe. 

# Others here are far better equipped to advise on it, as I don't have the benefit of recent hands-on experience in a well equipped lab with a VNA and fast enough DSO to make quantitative measurements of the effects of apparently minor chances to decoupling layout and component choice.  The principles are the same, but I haven't kept up with the effects of ever-shrinking SMD construction on its practical implementation.
Jajaho:
Thank you very much, Ian. I'll be sure to check it out as soon as I'm back in the lab.
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