EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: ilium007 on August 22, 2021, 03:32:46 am
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I am putting together a breadboard power supply (first SMD reflow board I have designed) and I am trying to work out why some of the same LDO circuit designs use input and output capacitors different to those specified in the manufacturer datasheets. I know the input one is there to prevent oscillations and the output one is to help with ripple (??) but how does one come up with 10uF / 0.1uF on the input and 22uF / 0.1uF on the output as shown in the Espressif design vs. the 4.7uF shown in the AP7361C LDO datasheet (https://www.diodes.com/assets/Datasheets/AP7361C.pdf (https://www.diodes.com/assets/Datasheets/AP7361C.pdf)) shown below?
(https://www.eevblog.com/forum/projects/selecting-input-output-capacitors-for-ldo-regulators/?action=dlattach;attach=1249750;image)
(https://www.eevblog.com/forum/projects/selecting-input-output-capacitors-for-ldo-regulators/?action=dlattach;attach=1249756;image)
On this design there are input / output capacitors on the LDO's but then a 'Power Filtering' bank of electrolytic capacitors, 10uF and 47uF, on the outputs of each LDO.
(https://www.eevblog.com/forum/projects/selecting-input-output-capacitors-for-ldo-regulators/?action=dlattach;attach=1249762;image)