parallel approximations

[aboubkr90]

Hello everyone!

I wrote a white paper and I need someone to review and help me refine it.

Thanks in advance.
Aboubkr Alrasheed.

[moffy]

If you want to patent as you stated in your PDF you shouldn't publicise before patenting, anything in the public domain can void a patent application.

[xvr]

Already invented  (More than 20 years ago)

https://www.analog.com/en/resources/technical-articles/understanding-pipelined-adcs.html

[aboubkr90]

Seems so.
But why are they using it for 100Msps?
With current fet latency, this thing can easily do 100Gsps!!

[tggzzz]

Seems so.
But why are they using it for 100Msps?
With current fet latency, this thing can easily do 100Gsps!!

See Keysight and LeCroy scopes. Also check the prices, and probably export regulations.

[xvr]

But why are they using it for 100Msps?

One reason already said by tggzzz - prices and export regulation.
Another drawback of such a design is that errors grow exponentially with each stage. Therefore, a very precise scheme is required, and this is the reason why the pipeline architecture uses not 1 bit, but 3-5 at each stage, and why its width is limited.

[aboubkr90]

I kept reading the article.
That's completely different.
The term "stage" in pipelined ADC is an ADC.
Here I'm talking about a single ADC with propagation between stages that are simple differential couples with Schmitt trigger outputs.
Bit error in this design happens when the stage to stage delay is a considerable portion of the input signal. Which is also completely different to the bit error in pipelined ADC.

[aboubkr90]

They're pipelining ADCs in series.
I'm talking about operating ADC stages in parallel.

[mawyatt]

If you want to see the SOTA in ADCs today (well back in ~2010 when we were still involved), check out the Non-Uniform-Sampling ADC (NUSADC) championed by Dr Mike Chen @ USC.

This technique makes the most use of a small number of voltage parallel comparators and takes advantage of advanced CMOS scaling by digitizing the precise time the input voltage crosses a comparator threshold, thus digitizing the input in both amplitude and time. This unique technique (amplitude and time digitizing) allows Post ADC conversion Anti-Aliasing Filtering in the digital domain.

Best