You dare summon me?!
Well, at a glance, I don't know exactly why it's doing that, could very well be the "startup" mode, yeah. They don't document it at all...
So -- I don't know if, or that, your particular issue can be solved; instead I think I would rather make a case against this chip entirely. So I'll explain that decision process.
So, just reading the datasheet:
https://www.ti.com/lit/ds/symlink/lm2621.pdf1. Introductions.
Headline boasts "high efficiency" and "low input voltage". Fair enough, it can be a challenging application and I don't know many regulators/converters offhand for this voltage range. (I don't shop for this spec range very often. I do recall seeing some LT parts, but c'mon, who's got money fo' dat?..)
First warning sign: "unique constant-duty-cycle gated oscillator". "Unique" isn't always a good thing. Probably nobody uses it, for a reason?
And if it's the good kind of "unique", why aren't they bragging about it as some silly patented/trademarked thing instead?
Assuming it's true that it works this way, then we can already guess some basic operation -- it must be hysteretic control, so it will have terrible output ripple (probably including weird subharmonic modes, depending on how it handles that hysteresis), and may have poor current control/protection.
Not really anything we can read into about the applications. None of these should be particularly tolerant of a voltage excursion like you're seeing. Maybe they intend it to be used with an LDO afterwards? That would be pretty rude...
2. Ratings and Characteristics.
Voltage limits are fine. Often enough you don't get current ratings with them anyway, so, whatever. Noteworthy they don't even specify ESD. I don't know that it's safe to assume a minimum 1kV HBM rating then.
But that FREQ pin rating. No voltage specified, and max 100uA into the pin (positive current is always into the pin) is awfully minuscule. Can it actually be damaged by 101uA? How does such an arbitrary limit arise? Surely that would be a functional not destructive limit? But they don't say anything about it in Recommended Operating Conditions.
V
IN_ST: is this just a behavioral characteristic, or does it relate to the
startup functionality mentioned later? There's no startup end voltage (or current or time) listed anywhere.
Nothing else really looks suspicious. The fixed duty cycle seems to support the "gated oscillator" claim, and yup, we see hysteresis. (Note that they don't say whether V
FB is rising or falling.)
There's also Fig. 8. How the load current is applied, isn't clear: is it an ideal sink, or a load resistor of equivalent value? It matters which kind!
At least, the fact that it's simply having a harder time starting up at high current, does seem to suggest there's nothing special: it simply has to work hard enough to get there, and if it can't (at low input), it doesn't.
Regarding Fig. 9, if we assume FREQ is a fixed voltage (relative to SGND), the fact that the 3.3 and 5V curves are offset this way, seems to support this assumption; and if frequency is proportional to FREQ current, then evidently V(FREQ) ~ 1.03V. Likely not a bipolar current mirror, but an NMOS current mirror could do. (That is, the pin is an NMOS, S = SS = GND, G = D = FREQ pin, i.e. "diode strapped". This voltage then goes to another NMOS G, with S+SS = GND, and its D will be a current proportional to I(FREQ), which in turn feeds an internal capacitor and oscillator in the usual way (multivibrator).) They do say BiCMOS, so it could be either kind after all.
It's still not obvious if this should make FREQ particularly sensitive or anything -- likely such a transistor doesn't need to be very big, but it could well have a zener or clamp diode across it which would provide adequate protection (particularly for ESD).
3. Description.
So here we come to the block diagram. It's a bit lacking, though also surprisingly detailed in certain respects, which is weird.
- FB into hysteresis comparator: supports the hysteresis characteristic from earlier.
- REF: sure, it'll have some kind of bandgap reference thingy inside. Hence the 1.24V V
REF, and clearly that gives the V(FB) thresholds (again, give or take hysteresis, direction isn't given). But why bother showing I
REF? It goes into an internal resistor, which is in ratio with another internal resistor; what the heck is the point? How can I know what these resistors are, or are doing? Why do I care that it's an I
REF, and not just a divider off V
REF or something? (Well, maybe it is...) And, if it is a current, then is that consequential to overall current consumption or anything? (Possible; likely something like this uses a handful of ~uA range current sources/sinks, and that could just be one of many. They'd all be driven by the bandgap, most likely.)
- SLEEP: why floating arrows to the other comparators? Why not draw it in directly? It's right there?.. And, what is this communicating, is this saying the comparators are gated by SLEEP? Is that an AND or OR logic? (My guess: they mean to disable power (bias currents, actually) to the relevant circuitry, hence, SLEEPing them. As long as the FB comparator is off, nothing else needs to run, anyway. But this notation is used to represent several functions so it would be nice to clarify, y'know?)
- OSC: well, your standard "I'm a logic block!" block. Go figure. Presumably it's something like, a constant current (mirrored from I(FREQ)) into a capacitor, into a comparator, so, making your basic multivibrator.
Interesting question: is the FREQ pin disabled when SLEEPing? Or its mirrors? It could well be that the answer is no, and SLEEP mode current has a component proportional to I(FREQ), in addition to the pin current itself I mean.
- Thermal shutdown: I don't think I've ever actually seen this detailed out like this before, actually. It's always just "temperature protection". As it happens, measuring a Vbe is a common and very reasonable way to measure temperature on-chip, and PTAT (proportional to absolute temperature) is available as part of the bandgap circuit. So, strange that they went to this detail at all.
- DRIVE: logic block #2. I guess BOOT is its power, so we get level shifting (presumably everything else is running at a possibly-lower VDD) and one or two stages of beefier transistors to drive the power NMOS.
The two parallel output transistors, by the way, are a pretty good way of sensing current. As long as the source voltages are close together (much less than Vds(on)), the sensed current will be a reasonably constant ratio of total current. And that ratio can be quite small because they can reserve like, a 1/100th of the transistor's area off to the corner to split off in this way. The resistor is free on a chip as well, of course; it's just going to be a bit of silicon or metal with Kelvin contacts going back to the sense amp / comparator.
How they sense current, isn't really very important (and, it's not like you can do much of anything about it in practice..). Generally, these sorts of things will have a fairly wide spread on Rds(on) anyway (see also: logic gate output current / resistance ratings, LDO current limit ratings, etc.), and basically it comes down to sensing Rds(on) or something related to it. Sometimes they'll draw it as a current sensor, or shunt resistor on the drain side; I suppose it's possible they could integrate a whole-ass like Hall effect sensor there, but most likely -- given the much higher common mode voltage at the drain side -- they're just lying, and really just doing it the easier way, and just showing it that way for clarity (so as to better say: here's output current, I guess?). Except when they really do have to do it the hard way, like, some controllers sense the V(SW) voltage of your external MOSFETs, to "measure" load current with Rds(on). Or DCR of the inductor (via an RC filter network, to attenuate most of the switching voltage across the inductor, leaving the resistance component, mostly).
Anyway, how they gate the oscillator is an interesting question. It's probably not simply ANDed with the comparator(s)? It could be latched, so the oscillator is always running, and it catches the next full pulse (you could tell by the pulses being timed consistently, while the bursts of output vary in pulses on/skipped). Or it might be held in a "primed" state, ready to fire (in which case, the time between bursts might vary continuously -- triggered by the hysteresis comparator falling below threshold). There might also be a holdoff time, which doesn't seem to be documented, and may or may not be helpful (that is, if V(FB) drops suddenly during an off slope, how soon after a burst can it turn back on? and if the answer is "instantaneous", then does that include during a normal low-pulse phase, so it can interrupt itself?).
- And, EN pin: literally nothing connected to it. S-M-R-T... (Given the wide VDD-referenced thresholds, it's probably safe to assume this is just any old CMOS input structure. Probably with ESD clamp diodes?)
(Oh, and I'm just now noticing, no leakage spec on FB or EN -- so who knows what value resistors are acceptable for setting these. This comes up here, as a leakage spec might be suggestive of input diodes. Reading datasheets is hard -- I forgot to think about these pin currents before, even while contemplating the nature of the FREQ current rating!)
Onward...
Second warning sign: 7.3.2. It seems to say it runs continuously in startup (so, regardless of V(FB)? even I(SW), Tj?) until 2.5V, but how does it know "output voltage", it doesn't even specify what pin is sensing this? (BOOT perhaps?) No logic is shown to implement this; plausibly OSC or DRIVE could do it. Again, anonymous logic blocks, who knows!
(And 7.3.4 seems to suggest current limit at least is latched. So, quite possible the other OSC inputs are latched too.)
And finally, Application. They give startup waveforms for the 5V boost, which doesn't show overshoot. Later they show a very similar SEPIC model, but no waveforms.
So, as the memes go -- by the way, it's a meme here that some here (cough
) despise the MC34063 -- hysteretic controls like this aren't great, and, at least this one doesn't suffer the worst problems of that particular chip, but it may well be crusty in ways that just can't be controlled from the outside; the documentation is just too poor to tell. And what it does tell, just isn't very impressive. (For reference, what I want to see in a low power controller/regulator is some manner of current-mode control. It can have slope compensation, it can have fixed internal (error amp) compensation, it can have pulse skipping, etc. Those are neither here nor there; current mode operation is several very good things at once however, which avoids many of the problems seen here.)
Also, it seems there's a LM2623A version; skimming the datasheet, it looks like they haven't cured almost any of the above oddities/bugs/problems, though.
So, all in all, I would decline to design in this particular chip, and recommend continuing shopping for something nicer.
Tim
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