Well for one i always noticed that higher efficiency SMPS's always clock beyond 500KHz ...
I can be wrong again i'm open to other ideas
There are two major contributions to SMPS power loss - switching losses and conduction losses.
Conduction losses are due to the parasitic resistances in the circuit: primarily the resistance of the copper in the inductors, and the drain-source resistance of the transistors when they're switched on. These scale with the square of the current, ie. they follow P=I^2*R.
Switching losses come from the fact that when a power transistor switches between the off and on states, it has to go through a brief period where it conducts but still has significant resistance. When it's off there's no current, and so no power loss. When it's on, the current is high but the resistance is quite small, so power dissipation is once again relatively small. However, during the transition between the two, there's both a high current and a high resistance, and since P=I^2*R, power dissipation can be briefly very high indeed.
The total switching loss equals the amount of energy lost per switching event times the number of switching events per second, ie. it's proportional to switching frequency.
Low switching frequency therefore tends to mean low switching losses, but the trade-off is that peak currents have to be larger - so conduction losses increase. With higher switching frequencies there are greater switching losses (ie. more lossy switching events per second), but conduction losses reduce because the peak currents in the circuit reduce.
For any design there's always a trade-off between conduction and switching losses, so it follows that there will be an optimum frequency that gives the best overall efficiency.