EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: rmacintosh on September 12, 2017, 03:57:06 pm
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I have built up a reference design for a SEPIC DC-DC. The design comes from Microchip involving their MCP1631HV PWM controller IC.
Ref. Design: http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=MCP1631RD-MCC2
(http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=MCP1631RD-MCC2)
After some simple mistakes and micro troubleshooting I have gotten my circuit to just barely work. All functions seem to be working, I can attach a battery to be charged and it all seems good until I make a few measurements. First of all temperature.
My switching MOSFET gets HOT! Peaking out at around 95C in roughly 30 seconds before I shut it down. Even the rectifier diode will reach almost 80C, and the coupled inductor reaches 50-60C along with the PWM controller IC as well. So I broke out the oscilloscope.
The third image is the PWM switching signal from the micro to the MCP1631HV - 500kHz / 25%
The first image is the slope compensation signal generated as input to the Current Sense / Vramp input pin of the MCP1631HV.
The second image is Ids in the switching FET, and the fourth image is my charging current to my test load battery.
Ids is measured across a pair of 0.22ohm sense resistors in parallel, which is also fed back to the current sense input of the MCP1631.
Charge current is measured across a 0.1ohm sense resistor just after the test battery.
I have some clearly massive oscillations at every switching transition. I have also obseved that my circuit will draw roughly 1.7-2A from my 12v DC input. I am not quite sure how to proceed here in damping those oscillations as I am not quite sure where the root problem lies.
Last picture is the schematic, it is exactly the same as the reference design linked above.
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Hard to say without seeing the layout. Also your probing may be enough to upset the circuit (passive probe ?)
Is your board anything like the eval board from Microchip?
http://ww1.microchip.com/downloads/en/DeviceDoc/51798a.pdf (http://ww1.microchip.com/downloads/en/DeviceDoc/51798a.pdf)
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Here are some layout images...
Would you suspect overheating & ringing/oscillations are caused solely by the layout scheme?
I have to admit, for this first revision I did not pay much attention to layout or to the layout scheme used in the ref. design for that matter.
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:o
Oh dear.
Your massive oscillations is part layout, part measurement technique.
The layout is bad. Like really bad.
High speed power switching layout rules, in prioritised order:
- keep the current loop area sizes tiny
- use well-placed decoupling caps, to further reduce the loop area, as seen by the highest frequency currents
- keep a reference plane very nearby, like 0.1 mm or less behind any and all power traces, which have high speed current commutations
Take a look at http://ww1.microchip.com/downloads/en/DeviceDoc/51791a.pdf (http://ww1.microchip.com/downloads/en/DeviceDoc/51791a.pdf), which is a four-layer board - look at how the power tracks have been arranged, the loop areas have been kept small.
Their usage of reference grounds on nearby layers leaves a great deal to be desired though. Getting the EMI under control would be an uphill battle with that layout.
To aid in developing your measurement technique, I suggest you look into horrendously expensive active probes, or keep on using the passive 10:1 probe and reduce it's loop area, which is formed by a way too long ground clip wire.
Go to something like this:
(https://www.eevblog.com/forum/projects/sepic-reference-design-problems/?action=dlattach;attach=350499)
That way it is not impossibly to capture signals fairly faithfully in excess of 100MHz, depending on the probe's basic capability in the first place.
Cheers!
/Ghydda
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ugh
try having a look at the reference layout and notice how the switching path is very tightly placed between input/output and away from the rest of the circuit.
Your inductor and FET are too far away from where the load connector and traces in the switching elements are too long. They probably also radiate into other parts of your circuit due to the long traces.
The sense resistor needs to be as close to the FET as possible with as little loop area as possible (also use much wider trace, at the sense resistor is a lot of rate of change of the current)
ps, I'm not a power electronic guy. I'm sure someone else will be better at pointing out problems
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ps, I'm not a power electronic guy. I'm sure someone else will be better at pointing out problems
Nah.
You pretty much nailed it :-+
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I don't know for sure, but you sure haven't made it easy to figure out...
(In the reactions that follow, imagine a cartoon acting it out. I like to overreact. ;D )
But first of all: please don't post incomplete schematics and pictures.
If you want easy answers, don't make it hard to find those answers!
Or, if you're shy about IP, there are many here willing to do a quick review-for-hire, or more. (I have a few spare hours knocking around, myself! ;) )
And the PCB drawings -- can you show silkscreen, soldermask and copper in the same view? Whole board, or at least whole power section. I'm constantly flipping between four tabs here, and the 3D view doesn't even cover the power area.
And describe, in detail, your load, source, operating conditions / setpoint, and so on.
Does it get hot just sitting there at no load, or is this full throttle (or more)? We don't know what you're trying to do with it.
Onward! ;)
1. There are miles between components.
Q2 connects on big long traces. C2 is way off to the side. Where even is C19?
Why is there another MOSFET (probably) in series with the diode? Why isn't this shown in the 3D picture (it's off to the right)?
What's C14? It looks big and important and nearby, but the top copper looks like it's not connected to the power area. I guess.
The current shunt resistors wrap around Q2 and are way out of the way. Wait, no, that's VCC to C13 and C16, but the shunts are still way off.
Also, Q1's 3D model doesn't look well positioned, oh and U3. Buh...
2. Ground. It's really bad.
You have top and bottom pours, that's a good start -- but the distance between where it's needed, and where it connects, is huge (like from Q2 drain via shunt resistors).
And it's full of holes: you've negated the whole bottom layer by chopping it up with routing traces. Run those WAY around the power section.
Then stitch it up with tons of vias. You should probably have 200 vias or more in a design this size. Over half will be ground vias!
Oh, oh no.
Oh no.
I've just realized, the top side isn't ground. It's 5V. You don't even have the possibility for a single stitched ground. The mere presence of the top fill is making the power section worse.
If it had been ground, at least you'd have a couple shorter grounds, but this is just... the current flow paths are labyrinthine!
3. No hooks for playing with EMI.
By that, I mean stuff like:
- Series gate drive resistor to Q2 (or ferrite bead, or resistor and diode, or whatever)
- R+C network across Q2 and D7
- More locations (also, closer locations) for optional bypass caps
- Extra LC filtering at input, output
Oh, oh no. I just realized GNDPWR is separate from GND, like, that it's separate at all is one thing -- but also that it's only tied, through the chip internally, and through two series capacitors. You could plug in a battery wrong, explode the chip and a few resistors, and have the whole thing just flapping in the rain, no connection between in and out. You don't want that as a failure mode. You want fuses to handle that.
It's maybe a little shocking that the chip didn't melt itself from the EMI [yet?].
So add that, too: the input and output are quasi-isolated, except not really, so each GND pin and each power pin needs to be filtered with respect to circuit ground. As is, it's a two-ended radiotransmitter!
4. Thermal.
95C might well be a perfectly reasonable design operating temperature; what did you design for?
Only a teeny trace on Q2 drain. No heatsinking to spread out the heat. (That said, the top and bottom pours do help a little with this.)
There's not much to do with inductors. Semiconductors are worth having big fat pads/pours on. Resistors too. Capacitors shouldn't get hot, but you want big fat conductors on them, too.
So, where to go?
I'm guessing you're pretty new to layout, at least this kind of layout.
First, rip everything up.
If it seems like a lot of work, that's all the more reason to do so -- rip it up ten times over, and gain experience with your tools, with the circuit. By the tenth time, you'll be ten times faster. (An experienced layouter would do this board in maybe a day or two.)
Get rid of GNDPWR. Use GND for all inputs, outputs and signals.
Rebuild it with a solid ground plane on the bottom, and ground pour on top. Use bottom routing as sparingly as possible. (Example: if two traces must cross, then near the crossing, use two vias and a short segment on the bottom side. This keeps the negative space around that trace as short as the segment. Then stitch around the top side ground with vias.)
Pack the components as close as you can. Minimize distance between R22/R24, Q2, L1 pins 3 and 4, C18, D7 and C19. That exact string of components is your switching loop. Add up the perimeter length. It should be no problem to have it around, oh, a half an inch, maybe less. You've probably got, hmm, three or four inches there? It's a huge difference.
Keep C13, C16 and R28/R30 nearby. That's a no-brainer since they're right at the ass end of L1.
Add a resistor in series with Q2 gate. Maybe 10 ohms. Not much, but a starting point. Try more, try less; try a diode in parallel (either direction), try a ferrite bead. The driver doesn't look to be too strong,
Oh, and don't go ham on the transistor or diode ratings. You don't want minimum conduction losses, you need low switching losses too. Looks like IRF7807 is pretty reasonable for a couple of amps, and not extreme on gate charge (17nC at 5V is 3.4nF equivalent; a 10 ohm driver will commutate this in about 70ns). Good choice, and B330A. (Though to be honest, it's hard to screw up schottky diodes, as long as the voltage and current ratings are appropriate. Outside of those basic options, there's very little freedom in schottky diodes -- voltage rating and voltage drop / leakage are a straight tradeoff. It's not like transistors where there's a whole spectrum of old and new parts, with different options, companions (transistor pairs, internal diodes..), and materials (GaN, SiC, Si).)
It may also be worth having an R+C across C18, because its voltage can oscillate. C18 resonates with L1's leakage inductance, and this resonant tank is in series between input and output, which can do weird things for your current sense (R28/R30), input and output ripple, and controller.
All of these values, by the way, can either be calculated directly, or at least hand-wavingly estimated. I'm not going to drown you in equations, but take comfort that they exist. :)
Cheers,
Tim
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Thanks guys,
I suspected as much. Being a reference design, I used the schematic and kept the parts the same so I figured it was likely for the problem to be my only contribution in circuit, the layout.
This is my first stab at a switching topology power supply so I knew it would take a few tries to get it right.
You guessed right, I don't currently have any active probes. Seeing their prices I may never own one for my home lab.
I like your suggestion Ghydda, ill make one of those ground wires for my probe.
I guess off to revision 2. I'll do some reading on layout techniques. When I get a new layout completed i'll revisit this thread for a second critique.
edit: awesome input T3sl4co1l!
you are spot on, I have no experience in switcher design and only slightly more in PCB layout.
I decided not to be easy on myself and pick a complicated project to learn basics with! |O
I can post anything you want to see, I was just trying to post the relevant part of the circuit I was troubleshooting. Its a battery charger, like the reference design is for but with additions such as load testing as well and datalogging and more V / I monitoring. Also getting rid of the buttons and full LED interface for a more user friendly display / readout.
This first spin is only built to be a charger as I want to perfect pieces of the circuit before adding features to it.
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Quick question...
I've been re-doing my layout following the layout of the reference design board gerbers as well as all of your suggestions.
My question is about ground. Specifically why the reference design board has separated signal ground (sgnd) from power ground (pgnd)
As in the image below from the ref. design schematic.
T3sl4co1l: referring to your comment Get rid of GNDPWR. Use GND for all inputs, outputs and signals.
What would be the reasoning why the reference design was done in this fashion? (separate signal and power ground then connect them together at a single point throught JP1)
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What would be the reasoning why the reference design was done in this fashion? (separate signal and power ground then connect them together at a single point throught JP1)
You're assuming they knew what they were doing!
Tim
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Here is my latest "REV3" layout. I think I have followed most of the suggestions.
I plan to find a bit more room to fit extra footprints for additional bypass/filter caps, and possible RC filtering around Q2 and D7 if needed.
Board is currently 3.3" x 2.25"
I need to get a working prototype first before I really can play a lot with tweaking with filtering out noise. The additional circuitry beyond what was copied from the Microchip MCP1631HV reference design are measures to include the ability to also load test a battery after/before charging. This controlled directly by Q5 and Q3. When charging batteries the Q5 gate would follow that of the ~shutdown pin on the MCP1631HV, with Q3 off. When load testing batteries Q5 off and Q3 controlled to a programmed discharge current. I ended up using the LT1999 in this case for current sense as the polarity across the sense resistor would change depending on charging or discharging the battery. I don't particularly like the push button/LED interface but I'll look to change that after I can verify the design on a bench.
Max. O/P voltage is 9v, and a input voltage range of 6-16v. The ouput is decided by programming the chemistry of the battery pack and number of series cells being charged. Charge current of 1.5A and a max output current of 3A. Variable discharge current with the same maximums.
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Improved by leaps and bounds! :o :clap:
Hmm, C19 missing label.
FYI, F1 and F2 will burn out long after Q5 or Q3. Transistors die in 10s or 100s of microseconds, fuses in 10s or 100s of milliseconds! Better to use a protected switch device, or put a hot-swap controller around them (if they're not being used for switching, which seems likely given the slow drive). There may also be a protected half-bridge device, perhaps for load switching (with a clamping option, hence the two switches), or for motor drive. Don't be afraid to contemplate alternative uses for specialized parts (like motor drivers). :)
C21/R35 goes nowhere, or, U5B for that matter! (This seems to be the only real mistake. :) )
At this point, most of what I'd change is just busy work, pushing things around to make neat rows, and optimizing trace widths and ground pour. Example: R41 and R50 aren't in a row. It doesn't make any difference, it just bothers OCD tendencies. ;D The pour by U6, just to the right, is broken by some vias, which could be spread apart. (Always mind the negative space around traces and footprints -- either leave enough space for copper to pour around an individual trace, or group multiple traces together.) The gate drive traces (connecting R49) can be thicker, to reduce stray inductance. Traces in general could be thicker, and clearance wider, maybe, but I'm not sure offhand if you're using 0805s or 1206s for most parts, so my sense of scale is off. Anyway, if it's 7/7 mils, that's fine, though I do prefer 10/10 if I really don't need anything finer.
Cheers,
Tim
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Yep, forgot the ground node at the other end of C21/R35 |O
U5B is an unused half of a dual opamp package.
I'll have to research something for a fuse alternative. Not familiar with hot-swap controllers, will have to read up on those.
I made measurements again with my original circuit eliminating the ground clip and using the wound wire on the probe tip, the measurements seem to be much better.
First is the new measurement of Ids of the switching FET
Second is the original measurement in the OP
Third is the new shunt measurement of output charging current.
Fourth is the original measurements in the OP
I am interested to see what differences a better layout provides on these same measurements. The circuit seems to be unable to properly regulate the current and seems to slowly climb until the current sense shuts down the controller and resets after about ~10-15 seconds. The efficiency seems low too, before resetting it's in the 65-75% range.
Thanks for your continued input, it has been invaluable!