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Serious ringing on U_GS in BLDC MOSFET bridge
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Jake the Snake:
Hi Everyone!
I am currently designing a motor inverter for a PMSM Motor and have some trouble with ringing on U_GS on the low-side MOSFETs when they turn off.
The specs for the inverter are as follows:
- ~29V Input from Lithium Battery
- Standard three phase design with three phase low-side current sensing
- Max. Phase current ist around 60A
- Full 4Q-Operation (forward and reverse with regenerative braking and accelerating)
- Incremental Encoder for rotor position sensing
- 28kHz switching frequency
I am using the following setup:
- STM32F415 with ST CubeMX Motor control Library
- TI DRV8323RS Smart Gate Driver and current sense amplifier
- 5mOhm Shunts below each low-side FET
- Nexperia BUK9Y7R2-60E MOSFET (60V, 7.2mOhm, 12nC, LogicLevel)
Please see the attached schematic and the layout for more details. To increase the cross-section in the positive supply rail (left side of layout) we have soldered some copper that reaches out directly to the MOSFETS. I know that the layout might not be perfect but we have some constraints regarding component placement. Phase terminals HAVE to be on the very left and mosfets should be on the right.
Exact problem description:
We encounter a lot of ringing on U_GS when we turn off the low side MOSFETs. I dont have a picture handy (no USB drive in lab to copy from scope), but the overshoot is around 100% of the supply voltage at 20A phase current. So U_GS spikes are around 60V at 30V Supply. As soon as I increase the current to lets say 30A, we blow one of the FETs (kind of expected).
The measurement was done with a Rigol DS1054Z with a probe and the clip on spring directly over drain and source. So no large ground loop or anything that could have influenced the measurement?
I have some questions regarding possible solutions...
- Decreasing gate drive current should help in theory (same dI, larger dt), but did not really help. I tried changing from 2A to 500mA. Will check with 100mA again tomorrow.
- Ceramic Caps from Supply+ to GND near the FETs should also help, according to most people. We already have plenty of caps there (5 * 4.7µF, 50V, X7R per phase) and I struggle to understand the theory why they should help?
- Changing dead time should have no effect. Right?
- Any Ideas to change the layout to decrease inductance?
- Any obvious mistakes I might have done?
Thanks and best regards,
Jake
Jake the Snake:
Hi Blueskull,
thanks for your reply!
I am not sure, if I understand you correctly. The gates are not driven by the battery rail directly! This would turn them on all the time.
I am generating 6 PWM Signals to the TI DRV8323 Gate driver. The DRV8323 has an integrated charge pump and takes care of the high-side MOSFETs.
Gate signals should be alright, as the bridge runs great on lower currents.
Thanks,
Jake
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