Any experience with ferroelectric NVRAMs?

[voja]

I bought some serial ferroelectric NVRAMs for some project which needs fast and frequent NV data storage. I wonder, if they are really so good, why aren't they used more frequently?

[mazurov]

You mean CMD (cylindrical magnetic domain)? Where did you get it and what's the part number?

[voja]

You mean CMD (cylindrical magnetic domain)? Where did you get it and what's the part number?

Bought them at http://store.comet.rs/Catalogue/Product/17127/
datasheet here: http://store.comet.bg/download-file.php?id=6665

[Howardlong]

They're used by Rigol in their test equipment ;-)

In an ongoing satellite project I am on they're used to maintain state in the case of a battery discharge, so far they have worked flawlessly in orbit on two satellites.

I am sure there are many other more mundane uses though. Zero wait time for writing, and, as good as darn it what can be considered infinite write cycles in some applications.

I would imagine the reason they're not used more universally is (a) price and (b) writes aren't quite infinite.

[PA0PBZ]

ferroelectric NVRAMs

Why does that make me think of core memory? 

[voja]

In an ongoing satellite project I am on they're used to maintain state in the case of a battery discharge, so far they have worked flawlessly in orbit on two satellites.

Good CV item, both for you and for NVRAMS

I would imagine the reason they're not used more universally is (a) price and (b) writes aren't quite infinite.

$1 is affordable price, especially for 10^14 writes and bus speed R/W. Seems to me like data storage I've been waiting for.

[wraper]

They have a drawback too. They loose data in higher temperature conditions, therefore cannot be pre-programmed before soldering.

[voja]

They have a drawback too. They loose data in higher temperature conditions, therefore cannot be pre-programmed before soldering.

Thanks, good to know that.
Didn't they have to note it in the datasheet?

[T3sl4co1l]

ferroelectric NVRAMs

Why does that make me think of core memory? 

Because you're absolutely positively 100% wrong, that's why...

But really, the ferroelectric and ferromagnetic effects actually share quite a lot in common, down to the level of raw physics -- so it's no accident.

Obviously, it's just a bit easier to charge capacitors on a chip, than to generate enough current to magnetize something.  Turns out the capacitors stop being useful below a certain scale, so the chips aren't exceptionally cheap or anything -- not like DRAMs where the feature size is absolutely minuscule.  But relative to depending upon a backup battery, or wearing out EEPROM/Flash, it's pretty neat stuff.

Tim

[Howardlong]

In an ongoing satellite project I am on they're used to maintain state in the case of a battery discharge, so far they have worked flawlessly in orbit on two satellites.

Good CV item, both for you and for NVRAMS

I'm semi-retired, I do this for the love of it, and any work I do do is on my account, i.e., I don't work for anyone, saves on the CV writing!

I would imagine the reason they're not used more universally is (a) price and (b) writes aren't quite infinite.

$1 is affordable price, especially for 10^14 writes and bus speed R/W. Seems to me like data storage I've been waiting for.

Although "normal" EEPROM is 1/3 of this price for the same capacity, so for medium to high volume it's going to make a significant difference on the BOM. I accept though, that for I2C applications, the write endurance is unlikely to be a problem. It might not be the same for SPi or parallel versions though.

[helius]

Another alternative are SRAMs with automatic Flash backup on powerdown.
Cypress makes these too: http://www.cypress.com/16MbnvSRAM/

[wraper]

They have a drawback too. They loose data in higher temperature conditions, therefore cannot be pre-programmed before soldering.

Thanks, good to know that.
Didn't they have to note it in the datasheet?

Have read a few datasheets, seems that some of them claim data to withstand reflow. Some of them clearly declare NO, most say nothing. http://www.ti.com.cn/cn/lit/an/slaa526a/slaa526a.pdf check pages 3 and 5, others may be worth to read too. Also seems that many datasheets specify data retention 10 years at 55^oC which temperature wise is pretty poor compared to flash and eeprom, time is not brilliant too.

[Kjelt]

Another alternative are SRAMs with automatic Flash backup on powerdown.
Cypress makes these too: http://www.cypress.com/16MbnvSRAM/

At €10.- a piece I do not see many companies putting that into any mass produced product but suited for a one of a kind or prototype.

[wraper]

Reading from FRAM requires applying an electric field across the crystal similar to a write. Depending on
the state of the crystal, it may (or may not) need to be repolarized, thereby emitting a large or small
induced charge. This charge is compared to a known reference to estimate the state of the crystal.
In the process of reading the data, the crystal that is polarized in the direction of the applied field loses its
current state [2]. Therefore, every read is accompanied by a write-back to restore the state of the memory
location.

Didn't know. Therefore seems that it is possible to destroy data by just reading it if power loss occurs.
EDIT: Ti in this document claim to be power loss proof, however worth to take into account with another devices. On the other side if automatic reprogramming occurs each time it is read, then data retention should not be an issue if just reading whole memory once it a while.

[Howardlong]

Another alternative are SRAMs with automatic Flash backup on powerdown.
Cypress makes these too: http://www.cypress.com/16MbnvSRAM/

ISTR these were made by SimTek originally. I used them about 20 years ago in a miniature Z80 based system, it meant that there was no need for both RAM and ROM chips, but you had to be careful that the stack didn't overflow or you toasted the ROM contents too, and it was back to plugging it into the programmer :-)

[Retep]

The previous company I worked used parallel FRAM's in their products because we needed frequent writes and relatively fast access times (to be able to cope with power failures and to able to resume when power was restored). The previous generation hardware used battery backed SRAM, but for obvious reasons we were happy to see those go. This system didn't need to store data in FRAM for very long periods of time, so I don't have any data about the long term data retention of FRAM. As far as I know we never had never had any issues with FRAM. Though At the time FRAM was relatively expensive when considering the price per bit, but given the total cost of the system that was not an issue for us.

[Pjotr]

It's just price and in some cases limited capacity. Most applications for small NV memory do not need fast write times and/or frequent updates. So a much cheaper EEPROM will do and outlast the product lifetime.

On the other hand the process for FRAM is not directly compatible with the CMOS process. It can be done but it is more expensive to incorporate FRAM in a micro controller than an EEPROM. TI has some I saw.

[Howardlong]

Reading from FRAM requires applying an electric field across the crystal similar to a write. Depending on
the state of the crystal, it may (or may not) need to be repolarized, thereby emitting a large or small
induced charge. This charge is compared to a known reference to estimate the state of the crystal.
In the process of reading the data, the crystal that is polarized in the direction of the applied field loses its
current state [2]. Therefore, every read is accompanied by a write-back to restore the state of the memory
location.

Didn't know. Therefore seems that it is possible to destroy data by just reading it if power loss occurs.

As you may imagine, I spent a lot of time testing for this both on prototypes and in the cleanroom during integration and final checkout of our satellites prior to launch. We did have an error,to do with data corruption in the design but that was not the FRAM itself, it was to do with the way a CPLD would actively (and incorrectly) execute a bogus write cycle during power down. In the end we glued a resistor onto the board (with very special glue of course) to force a write protect on the FRAM in this event. It was slightly more complex than that, but that was the basis of the fault.

I think that you can be sure that these devices work, and do not destroy data, in the scenario you specify.

[T3sl4co1l]

Yeah, data destruction occurs during the first... nanoseconds? of a read cycle, and is immediately written back.  Same as with DRAM... of course, DRAM loses its mind when power goes down (although not instantly or totally, especially when kept cool), which is the difference.

Tim

[dannyf]

ferroelectric NVRAMs

FRAM?