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Offline OM222OTopic starter

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Sharing decoupling capacitors
« on: May 16, 2019, 11:01:09 pm »
I think I've been using too many decoupling capacitors in my designs, with each chip getting a 100nF decoupling capacitor of its own.
sometimes two chips are as close to each other as physically possible, for example: an op amp and a voltage reference both powered from a 5v supply. A lot of times the chips work well even without any decoupling like Dave showed in his megatron computer video. I was wondering if two chips that are close to each other (usually SOIC-8, so very very close) can share the same 100nF decoupling cap or if I should bump it to let's say 1uF for good measure if I decide to make it shared.
 

Offline golden_labels

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Re: Sharing decoupling capacitors
« Reply #1 on: May 16, 2019, 11:37:29 pm »
Decoupling capacitors on power lines are there not only to protect an IC against noise and trace inductance effects, but also to protect the rest of the circuit from that IC. This works both ways. As an example see separated power inputs for ADC/DAC and digital parts in microcontrollers. You are literally separating the chip from itself with a pair of decoupling capacitors, because the digital section can cause so much noise that it will affect the analog part.

You may remove as many caps as you wish. It’s not like they’re strictly required for chips to work properly. All that happens, when you remove a capacitor, is going outside manufacturer’s spec. Here be dragons. Just that and nothing more. It’s a matter of risk you want to take. Can you test the circuit well enough to show it will work? Remove them. Can you accept the risk involved? Remove them. But there is no general silver bullet solution: you will need to experiment, test and understand what happens in your circuit without a cap.

I am myself not believing, that I’ve said the above. For me, as a software developer aiming to write good software, the above is a blasphemy. ;)
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Online DaJMasta

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Re: Sharing decoupling capacitors
« Reply #2 on: May 16, 2019, 11:43:46 pm »
The problem is the 100nF guideline is generally for digital stuff and is only a guideline... there are instances where following it can actually cause issues, and there are instances where you can get away with a tiny fraction of the decoupling caps.

So unless you expect the amp to be using its maximum slew rate a lot or sourcing a lot of current, it probably won't be generating as much noise as a fast toggling digital circuit, but since it's analog stuff which is generally going to be more effected by noise, why not "compromise" and use a couple of different values, maybe a 100nF and a 1uF, maybe a 100nF and a 10nF.  Having your reference bypassed is important, and having a reservoir of charge there is probably a good idea (maybe take a look at the datasheet recommendations), and while the circuits at this node probably won't be generating much noise on their own, they will be sensitive to smaller fluctuations in supply voltage than a digital circuit, so I wouldn't skimp on the bypassing caps which help filter the rails at the point where the current is needed.

Just using a single 1uF cap would mean you had a larger charge reservoir to dampen transients, but it would also mean that the impedance of the capacitor will be higher than a 100nF or smaller cap at high frequencies, so only going with a low frequency, larger value bypass cap would actually be less effective at removing high frequency noise on the power rail than a small one.
 

Online ataradov

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Re: Sharing decoupling capacitors
« Reply #3 on: May 16, 2019, 11:44:01 pm »
One per chip is not sufficient in many cases. You need one per power supply pin.

This does not apply to slow circuits. But it starts to matter a lot on chips with PLLs and other fast logic.

I would definitely at least put a footprint for one capacitor per device. You don't have to populate it if you find it unnecessary later on.
« Last Edit: May 16, 2019, 11:47:18 pm by ataradov »
Alex
 

Offline OM222OTopic starter

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Re: Sharing decoupling capacitors
« Reply #4 on: May 16, 2019, 11:48:45 pm »
most of my designs are dc with very few transients, and even then not at high frequencies. the board size is pretty small too 10x6.8cm and the tracks are no longer than a few CM. I can understand why multiple ones would be required for high speed circuits but I'm assuming sharing them between chips is fine in my case?
 

Online ataradov

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Re: Sharing decoupling capacitors
« Reply #5 on: May 16, 2019, 11:53:46 pm »
It will probably work, whether it is fine depends on the circuit. For very slow stuff, it is probably be fine. But again, why not put a footprint and not populate if if see that it is not needed.

Also by "slow" you need to understand limited slew rate, not the rate of events. If you are switching something once a second, but with a high current driver, it is still a fast circuit, that will generate transients.

Even typical 400 kHz I2C drivers are reasonably "fast" in this regard to meet the requirements of the I2C specification. 
Alex
 

Offline OM222OTopic starter

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Re: Sharing decoupling capacitors
« Reply #6 on: May 17, 2019, 12:12:11 am »
the problem is the footprint itself. the board is so tightly packed that should either drop the capacitor size to something like a 0402 which I can't solder by hand, or use a 1uF 0603 and share it between 2 - 3 devices. I know I should have purchased the enclosures after I designed the PCB, not before, but I think sacrificing a few decoupling caps can save me here since the board is mostly routed.

also since you brought up I2C, I didn't use pull ups for the exact same reason (not enough space) and after checking with a scope, the edges couldn't be any more square even with the fastest mode. I'm assuming it's due to short traces which means pretty much no parasitics.
« Last Edit: May 17, 2019, 12:38:04 am by OM222O »
 

Online ataradov

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Re: Sharing decoupling capacitors
« Reply #7 on: May 17, 2019, 12:50:24 am »
couldn't be any more square
And that's exactly the problem.  Those square edges tend to create all sorts of ground bouncing when the chips are not properly decoupled.

If you are really strapped for space, then it is a reasonable risk to take, but it is still a risk. The worst case - you will have to redesign the board a bit.
Alex
 

Offline langwadt

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Re: Sharing decoupling capacitors
« Reply #8 on: May 17, 2019, 12:58:53 am »
the problem is the footprint itself. the board is so tightly packed that should either drop the capacitor size to something like a 0402 which I can't solder by hand, or use a 1uF 0603 and share it between 2 - 3 devices. I know I should have purchased the enclosures after I designed the PCB, not before, but I think sacrificing a few decoupling caps can save me here since the board is mostly routed.

also since you brought up I2C, I didn't use pull ups for the exact same reason (not enough space) and after checking with a scope, the edges couldn't be any more square even with the fastest mode. I'm assuming it's due to short traces which means pretty much no parasitics.

I2C is open-drain it requires pull-ups somewhere

 

Offline OM222OTopic starter

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Re: Sharing decoupling capacitors
« Reply #9 on: May 17, 2019, 01:05:48 am »
the MCU has some built in, but I think they are 50k which is normally too large and fast I2C recommends something like 2k pullup, but doesn't seem to be the case on my board  :-+
 

Offline golden_labels

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Re: Sharing decoupling capacitors
« Reply #10 on: May 17, 2019, 01:29:57 am »
Is the microcontroller THT DIP by any chance? Use a DIP socket and you get a lot of space under the chip itself.
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Offline Nerull

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Re: Sharing decoupling capacitors
« Reply #11 on: May 17, 2019, 02:02:24 am »
A perfect square wave consists of an infinite series of increasingly higher frequency sine waves. Those 'nice square edges' are a sign that your signal is, in fact, high frequency and high speed. A slow rise time will round the edges.
 

Offline T3sl4co1l

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Re: Sharing decoupling capacitors
« Reply #12 on: May 17, 2019, 02:03:23 am »
Decoupling is overblown.

In a 2-layer design, you rarely have anything fast enough, or powerful enough, to require more than infrequent decoupling.  When you do (switching regulators being the most common case), simply include them as part of the local subcircuit design -- don't assume an ideal skyhook is there to save you.

In a multilayer design with internal planes, you may have things fast or powerful enough to require frequent bypassing.  But you also have the nearly ideal interconnect that is the power plane.  Bypass caps almost anywhere on the board look equivalent.  It doesn't much matter where you place them.  If a chip needs very serious bypassing, caps can be placed beside the pins, or on the opposite side, under the component (e.g. BGAs).  For the most part, caps on the opposite side, or not connected as directly to the pins as is possible, might as well not be there -- and here I don't mean that they can be removed entirely, but that they aren't acting locally, and can move around just about anywhere.  They may however be removable, depending on whatever's on the planes, and what supply impedance is required.

By the way, the ideal connection to an adjacent pair of pins*, is with a pair of vias (to internal plane) on one side, and the decoupling cap on the other.  This way, the pins see two impedances in parallel: the cap and the plane.  You can equally well use no cap and two pairs of vias.  Or two caps and no vias, except that you can't put a cap underneath a component, so...

Note that a cap on the opposite side (say in a 2-layer build) is farther away than a single cap on the same side, so doesn't do much.  Single caps are fine in that case.

*VDD/VSS pairs are common, say with MCUs and such, for this reason -- lower ESL.  There's usually a bunch of pairs spread around the chip -- all should be connected, if not to planes then to adjacent caps.  Whether any given pair of pairs can be connected to a single common cap, say -- depends.  (Sometimes, these pairs are temptingly close together!)

...

Excessive bypasses: I think it's more psychological (read: not based on electrical theory).  "No one got fired buying IBM", you know?  Throw in "too many" bypass caps and you have the same situation.

It's not hard to analyze these networks, and justify ones' use of decoupling capacitors.  Transform pin lengths, trace lengths, via lengths and component body lengths into inductances, and construct the network from the layout topology (don't forget ESR of the various capacitors).  This is an easy (under an hour?) SPICE exercise, and allows you to play with virtual placements and types (i.e., vary C and ESR and see how the transient response changes; vary the topology, or the trace lengths, etc.).

Or once you understand the underlying equations (it's all about poles and zeroes), it's possible to hand-wave through this and estimate what C and ESR is needed to terminate a given branch, or what topologies are easier to terminate, or can give better filtering or isolation between sections.  Then SPICE it anyway for verification, then hook up a pulse generator to a real board and demonstrate it experimentally. :D

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Offline OM222OTopic starter

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Re: Sharing decoupling capacitors
« Reply #13 on: May 17, 2019, 03:51:43 am »
Is the microcontroller THT DIP by any chance? Use a DIP socket and you get a lot of space under the chip itself.
unfortunately the board is fully SMD. MCU is in a TQFP-32 package.

Also thank you for the detailed explanation TIM. very helpful.
 

Offline OwO

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Re: Sharing decoupling capacitors
« Reply #14 on: May 17, 2019, 05:12:08 am »
On even a 4 layer board it's not possible to have an effective power plane because with the typical stackup in1 is very far from in2 (over 1mm). I stand by my advice to put decoupling caps on the bottom side right underneath the IC, because putting them on the top side obstructs routing and unless you go to 0201 there is no way you can put them closer to within 1.6mm of the IC and still be able to route out all the other pins. In a BGA the power pins can be very far from the edge, so not putting caps on the bottom is bad advice.

I have done boards with Zynq and DDR3 memory on 4 layers, and in general do not use buried power planes for the purpose of decoupling. When you do have a power plane you have to stitch it at regular intervals especially close to the current sinks (noise sources). The "inductance" seen between two planes can be significant at points not close to stitching caps, and this can be seen experimentally but impossible to simulate in spice.
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Offline schratterulrich

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Re: Sharing decoupling capacitors
« Reply #15 on: May 17, 2019, 05:19:55 am »
In the past I was often unsure about the right decoupling capacitors.

We then introduced a software in the company that simulates the impedance of the power delivery network. That made things easier.
Depending on your transient current consumption and your voltage ripple allowed you can say that e.g. 100 mOhm up to 100 MHz would be sufficient.

As mentioned by Tim you can analyze the decoupling caps and planes, so I have written my own software.
It's a big help for supply systems with power planes but maybe it can help in your case too
You can find it at https://leiterplatte.jimdo.com/pdn-sim/

The result can look like this


Best Regards
Ulrich


 
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Offline ogden

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Re: Sharing decoupling capacitors
« Reply #16 on: May 17, 2019, 05:31:48 am »
Decoupling is overblown.

If you consider signal integrity, then indeed. Most "2-layer" circuits will continue operation without single decoupling capacitor. On the other hand small & seemingly innocent uC without proper decoupling can trash radiated EMC tests easily.
 

Offline Zero999

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Re: Sharing decoupling capacitors
« Reply #17 on: May 17, 2019, 08:02:09 pm »
You quite likely don't need a decoupling capacitor for every IC, especially those which sit in a steady state.

I've just built a circuit with no decoupling and it works perfectly. It's a voltage reference to give 5V and 10mV out for adjusting a DC amplifier. It's very simple, just LM4040-N-2.5 and current limiting resistor, connected to an OP07 op-amp with a gain of two and a potential divider. The output voltages are trimmed by adjusting a couple of potentiometers. There is no other high speed circuitry on the board or nearby and is powered by a 15V linear power supply module, so no decoupling capacitors are required, because there is no AC in the circuit.
« Last Edit: May 17, 2019, 08:39:16 pm by Zero999 »
 
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Offline ddavidebor

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Re: Sharing decoupling capacitors
« Reply #18 on: May 17, 2019, 08:12:02 pm »
I think I've been using too many decoupling capacitors in my designs, with each chip getting a 100nF decoupling capacitor of its own.
sometimes two chips are as close to each other as physically possible, for example: an op amp and a voltage reference both powered from a 5v supply. A lot of times the chips work well even without any decoupling like Dave showed in his megatron computer video. I was wondering if two chips that are close to each other (usually SOIC-8, so very very close) can share the same 100nF decoupling cap or if I should bump it to let's say 1uF for good measure if I decide to make it shared.

Is this a commercial product that needs to pass emi testing?
How many layer is your board and what stackup do you have?
David - Professional Engineer - Medical Devices and Tablet Computers at Smartbox AT
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Offline iMo

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Re: Sharing decoupling capacitors
« Reply #19 on: May 17, 2019, 08:23:03 pm »
Decoupling is important and usually ignored. Any today's mcu has got 5ns edges. Even a blinking with an led produces transients.

And even a fully quiet DC circuit can go easily weird when irradiated by an EMI.

A friend of mine is running an EMC lab and even BIG players sometimes come with something which does not pass the basic test because of a missing 1cent capacitor.

That would apply to the above 5V reference source too :)
« Last Edit: May 17, 2019, 08:30:35 pm by imo »
Readers discretion is advised..
 

Offline ogden

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Re: Sharing decoupling capacitors
« Reply #20 on: May 17, 2019, 08:32:15 pm »
It's very simple, just LM4040-N-2.5 and current limiting resistor, connected to an OP07 op-amp with a gain of two and a potential divider.

Nice example. Slew rate of OP07 is 0.3 V/us. Decoupling of such a slow opamp is useless waste of capacitors :)
 

Offline iMo

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Re: Sharing decoupling capacitors
« Reply #21 on: May 17, 2019, 08:41:06 pm »
You can find it at https://leiterplatte.jimdo.com/pdn-sim/
I've been searching since ever after a tool which imports the Eagle PCB file and calculates impedancies/capacitancies/inductancies/resistancies of the top and bottom tracks.
Readers discretion is advised..
 

Offline OM222OTopic starter

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Re: Sharing decoupling capacitors
« Reply #22 on: May 17, 2019, 09:46:35 pm »
I think I've been using too many decoupling capacitors in my designs, with each chip getting a 100nF decoupling capacitor of its own.
sometimes two chips are as close to each other as physically possible, for example: an op amp and a voltage reference both powered from a 5v supply. A lot of times the chips work well even without any decoupling like Dave showed in his megatron computer video. I was wondering if two chips that are close to each other (usually SOIC-8, so very very close) can share the same 100nF decoupling cap or if I should bump it to let's say 1uF for good measure if I decide to make it shared.

Is this a commercial product that needs to pass emi testing?
How many layer is your board and what stackup do you have?
It doesn't require EMI testing and it's a simple 2 layer board. I can see people are at quite a large disagreement. Some say decoupling isn't even required and some say it's not done enough / properly. I guess I have to test it by removing the caps and checking with the scope to see the differences?
 

Offline thm_w

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Re: Sharing decoupling capacitors
« Reply #23 on: May 17, 2019, 10:04:27 pm »
It doesn't require EMI testing and it's a simple 2 layer board. I can see people are at quite a large disagreement. Some say decoupling isn't even required and some say it's not done enough / properly. I guess I have to test it by removing the caps and checking with the scope to see the differences?

It depends on the design and the requirements. A schematic or board photo might help a bit (it seems hard to see a case where you can't fit in one 0603 per IC).
But your plan is a good one, measure, remove the capacitor, measure again.

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Offline T3sl4co1l

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Re: Sharing decoupling capacitors
« Reply #24 on: May 17, 2019, 10:07:24 pm »
You quite likely don't need a decoupling capacitor for every IC, especially those which sit in a steady state.

I've just built a circuit with no decoupling and it works perfectly. It's a voltage reference to give 5V and 10mV out for adjusting a DC amplifier. It's very simple, just LM4040-N-2.5 and current limiting resistor, connected to an OP07 op-amp with a gain of two and a potential divider. The output voltages are trimmed by adjusting a couple of potentiometers. There is no other high speed circuitry on the board or nearby and is powered by a 15V linear power supply module, so no decoupling capacitors are required, because there is no AC in the circuit.

https://www.eevblog.com/forum/projects/sharing-decoupling-capacitors/?action=dlattach;attach=739044;image

There is AC in the circuit whether you intend there to be or not!

Run that from some longer cable for example, and the opamp is likely to oscillate.  Dynamics exist whether there is an apparent (large scale) signal present or not!  Thermal noise is sufficient to push a system over the edge from an initial resting position (which may accidentally be an unstable point).

This, incidentally, is why it's often hard to get SPICE oscillators to start.  There's no noise unless you've specifically placed noise sources.  And even so, if the amplitude is below the tolerance settings, it may simply be ignored and smoothed over.

And so, this is the other intent behind good decoupling -- to isolate the on-board network from the outside world.  And to do this, resistance is necessary.  That is why we dampen or "swamp" resonances with ESR, and often it's as simple as a 100uF electrolytic somewhere. :)

Tim
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Electronic design, from concept to prototype.
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