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Sharing decoupling capacitors
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OwO:

--- Quote from: T3sl4co1l on May 17, 2019, 10:15:29 pm ---How does the absolute distance come into this?

--- End quote ---
Distance between power and ground plane determines the impedance seen at a given point between the two planes that isn't very close to a decoupling cap. The simulation tool linked by schratterulrich should be able to show this.

Onchip decoupling is the reason chips still work at all considering the huge bondwire inductance and the interposer wire length (for BGAs), so usually it's not critical to get down to the last mm of distance between cap and pins, hence why caps at the bottom side of the board is just as good for high speed designs (Zynq) without needing a power/gnd plane pair.
OM222O:
Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB:


they just went to town with ceramic caps for the VRM since the pick and place was going to take care of it.
floobydust:
Decoupling capacitors were explained in university, based on TTL gates switching and DIP packages and short PCB traces to a through-hole capacitor.
TTL totem-pole shoot-through current was the main issue, and based on total inductances of the capacitor, pcb traces, DIP package, around 0.01uF was enough to stop glitches on 5V rail. Using 0.1uF was 10x needed and afforded extra insurance for larger parts like SRAM and became common practice.

But on cell-phone modules +4V rail I see multiple staggered values like 10pF, 33pF, 100pF, 1nF, 10nF, 100uF on factory datasheets. TX currents to 1A on 800-1900MHz up, I guess the SRF of each decoupling capacitor needs to overlap.
iPhones are well engineered this way too, check some of their schematics.
schratterulrich:
For critical projects we don't use 100nF caps at every IC anymore in our company. Instead we use very thin core and prepreg material with a thickness of 50µm for every power rail. The disadvantage is that we usually need 12 to 16 layers. Then we place capacitor groups around the board evenly distributed. Due to the thin core material and the very low inductance of the resulting plane pairs the caps don't need to be placed ACAP to the ICs. The values of the capacitors have to be determined with a simulation.
We have very good experience with EMC and ESD with this approach.
Also the routing is easier especially because we need the space around the ICs mostly for series termination resistors.

Of course for boards with lower layer counts we still use conventional decoupling caps at every IC and I would strongly recommend them.
It is difficult to test your design for all conditions even if it works in the lab.
rstofer:

--- Quote from: OM222O on May 17, 2019, 12:12:11 am ---also since you brought up I2C, I didn't use pull ups for the exact same reason (not enough space) and after checking with a scope, the edges couldn't be any more square even with the fastest mode. I'm assuming it's due to short traces which means pretty much no parasitics.

--- End quote ---

I2C pins are open collector or open drain.  Section 3.1.1 here:

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

What is providing the pull-up for your test?  Something is doing it and shouldn't be.
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