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| Sharing decoupling capacitors |
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| ataradov:
--- Quote from: rstofer on May 18, 2019, 04:24:02 pm ---What is providing the pull-up for your test? Something is doing it and shouldn't be. --- End quote --- He already replied - internal pull-ups of the MCU. And they do work fine for short traces in my experience too, even though they are typically an order of magnitude higher than recommended. |
| T3sl4co1l:
--- Quote from: OwO on May 18, 2019, 02:11:00 am --- --- Quote from: T3sl4co1l on May 17, 2019, 10:15:29 pm ---How does the absolute distance come into this? --- End quote --- Distance between power and ground plane determines the impedance seen at a given point between the two planes that isn't very close to a decoupling cap. The simulation tool linked by schratterulrich should be able to show this. --- End quote --- Ah, but that's the third variable: distance! Inductance is always proportional to a volume ratio length. Or whatever it's called. To get the resistance of a solid, you take resistivity and divide by (cross-sectional area divided by longitudinal length). Same with inductance, where the area is that of the transmission line cross section (with a geometry factor of course), and the length is the length of the line. If we consider the inductance of a via into a plane, we can look at the inductance of a cylindrical cavity resonator, where the height is very short (so we can ignore edge effects), the inner radius is the diameter of the via, and the outer diameter is an arbitrary boundary. The boundary might be a wall of nearby vias (which again, for the power planes case, are vias to bypass caps), or the edge of the board (in which case the inductance acts in series with the plane capacitance, and we have a series resonance -- this is the lumped equivalent of the first standing wave mode between the planes), or to infinity if we wish to look at the asymptotic case. We use a cylindrical model, because we're looking at waves propagating from the via radially. Of course, if we have vias placed in this plane in arbitrary locations, their radial "fields of view" will overlap, and for example the inductance between two vias will be approximately the sum of both inductances, when outer diameter = distance/2, but there will be some mutual inductance between them as well (where outer diameter > distance/2), so we could draw a more detailed diagram accordingly. When the problem is set up as such, and the integral is solved, we get a logarithmic result: L = k * mu * h * ln(D/d) (I forget exactly if there is a constant of proportionality there; it may be k = 1, and also mu = mu_r * mu_0 but we can just use mu_0 for PCB because mu_r = 1...) Putting in typical values, we expect figures close to the usual via inductance figure itself, and since it varies logarithmically with D, we aren't so worried about how far away things are, beyond some point. We do get some advantage when a capacitor can be placed at a distance less than h away from the via (on same layer), but if not (or when not required), the added inductance of the plane to other nodes is quite small. Take for example mu = 1.257 nH/mm, h = 1mm, D = 20mm and d = 0.3mm. The log is 4.2, so it's like having a 4.2mm tall via, and L = 5.3nH. Not much, comparable to a few mm of trace length! I would be quite happy doing this for an MCU, which might draw a rate of 100mA/5ns (say by toggling a full port of LEDs). Times 5.3nH, this is a peak voltage (at internal VCC) of only 106mV, a few percent out of a 3.3V supply. And indeed, I do this regularly, and the MCU has never shown aberrant behavior. :-+ We can also consider a ring of vias, or any arbitrary clustering of vias with an equivalent diameter of d, and apply this formula. (Or use this formula in reverse to solve for the equivalent diameter of that pattern, given another calculation or measurement of the inductance.) This of course demonstrates why multiple vias are valuable (a circle of vias of say d = 2mm in the same setting gives about half the inductance in the same case). Regarding mutual inductances -- crafting a lumped equivalent of a distributed structure (following a transcendental function, at that) would be very tough, so if we need detail quite on that level, we might as well just break it up into a grid and approximate it that way; hence, the analysis program above, of course. :) Tim |
| NorthGuy:
--- Quote from: OM222O on May 18, 2019, 04:17:31 am ---Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB: --- End quote --- If you have millions of FETs simultaneously switching at tremendous speed, you do need lots of capacitors. And they have to be very fast and therefore small. Thus it's really hard to gather enough capacitance. |
| DaJMasta:
--- Quote from: NorthGuy on May 19, 2019, 04:13:32 am --- --- Quote from: OM222O on May 18, 2019, 04:17:31 am ---Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB: --- End quote --- If you have millions of FETs simultaneously switching at tremendous speed, you do need lots of capacitors. And they have to be very fast and therefore small. Thus it's really hard to gather enough capacitance. --- End quote --- It's also a model that's advertised for overclocking, so they guild the lily with decoupling caps and VRM phases with the hopes that overdoing it will help keep things stable above normal clocks. They know that people who are spending for the top card with the intention of overclocking will buy based on good results they hear about, so if they can go the extra mile in their design to overcome potential overclocking limitations with a dollar of extra caps and pick and place time, it's definitely in their interest. |
| LukeW:
A picture of your layout would be more significant than the schematic. It's all about minimising the parasitic inductance, and getting those decoupling capacitors as close as possible to the loop on the IC where the current is actually going. "Electromagnetic Compatibility Engineering" (H.W Ott) has a great treatment of decoupling capacitors. |
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