Author Topic: Sharing decoupling capacitors  (Read 7728 times)

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Offline T3sl4co1l

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Re: Sharing decoupling capacitors
« Reply #25 on: May 17, 2019, 10:15:29 pm »
On even a 4 layer board it's not possible to have an effective power plane because with the typical stackup in1 is very far from in2 (over 1mm).

How does the absolute distance come into this?


Quote
I have done boards with Zynq and DDR3 memory on 4 layers, and in general do not use buried power planes for the purpose of decoupling. When you do have a power plane you have to stitch it at regular intervals especially close to the current sinks (noise sources). The "inductance" seen between two planes can be significant at points not close to stitching caps, and this can be seen experimentally but impossible to simulate in spice.

Stitching?

Oh, you mean bypass caps, to serve the same purpose as stitching vias in a multi-layer-ground design*?  Yeah.

*Which, for those that don't know, is the typical 2-layer approach.  Pour ground, route everything else (including supplies), stitch grounds frequently.

Most extreme example of that I've seen, think it was a Sun server, the CPU module.  Absolutely fucking plastered with caps, from the VRM to the CPU.  The CPU also had a lot of ceramic LGA caps on itself, as well.  The effect is to make a mixed distributed-lumped transmission line with an extremely low impedance.

Have to wonder if they really needed all that, or if they just didn't give a shit as far as analyzing the PDN onboard the chip itself, and hacks like phasing different regions, or what.  It's my understanding, modern chips get by just fine with onboard networks, so that the external circuit only has to deliver modest changes (bandwidth in the upper 10s of MHz), and all the scary high frequency stuff is handled on die, and on the interposer.  Surely the same approaches would've been applicable, but they probably didn't think it would be worth the time to analyze, considering the low quantity and massive sale price of those beasts.

Tim
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Offline T3sl4co1l

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Re: Sharing decoupling capacitors
« Reply #26 on: May 17, 2019, 10:23:13 pm »
A friend of mine is running an EMC lab and even BIG players sometimes come with something which does not pass the basic test because of a missing 1cent capacitor.

Heh.. I would dare say size is a counter indication to competence (the Peter Principle).  With a low correlation, mind.  Did a job with a large electrical supplier: after spending several years working on this project, their power supply still blew emissions by a huge margin.  The board was basically Swiss cheese, no planes whatsoever, ground was a cluster.  I tore up existing routing, optimized component placement, put in two solid planes, and reduced emissions by >20dB (depending on frequency range in question).

Tim
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Offline Zero999

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Re: Sharing decoupling capacitors
« Reply #27 on: May 17, 2019, 10:55:57 pm »
You quite likely don't need a decoupling capacitor for every IC, especially those which sit in a steady state.

I've just built a circuit with no decoupling and it works perfectly. It's a voltage reference to give 5V and 10mV out for adjusting a DC amplifier. It's very simple, just LM4040-N-2.5 and current limiting resistor, connected to an OP07 op-amp with a gain of two and a potential divider. The output voltages are trimmed by adjusting a couple of potentiometers. There is no other high speed circuitry on the board or nearby and is powered by a 15V linear power supply module, so no decoupling capacitors are required, because there is no AC in the circuit.

https://www.eevblog.com/forum/projects/sharing-decoupling-capacitors/?action=dlattach;attach=739044;image

There is AC in the circuit whether you intend there to be or not!

Run that from some longer cable for example, and the opamp is likely to oscillate.  Dynamics exist whether there is an apparent (large scale) signal present or not!  Thermal noise is sufficient to push a system over the edge from an initial resting position (which may accidentally be an unstable point).

This, incidentally, is why it's often hard to get SPICE oscillators to start.  There's no noise unless you've specifically placed noise sources.  And even so, if the amplitude is below the tolerance settings, it may simply be ignored and smoothed over.

And so, this is the other intent behind good decoupling -- to isolate the on-board network from the outside world.  And to do this, resistance is necessary.  That is why we dampen or "swamp" resonances with ESR, and often it's as simple as a 100uF electrolytic somewhere. :)

Tim
I can see your point, but it would have to be really bad for that circuit to oscillate. The construction wasn't perfect: stripboard with a 200mm twisted pair power cable and it worked perfectly.

Look at lots of really old analogue circuits, note that decoupling is either scant or non-existent and they worked perfectly well. It's only become really important since digital circuits which draw high current spikes became popular. Even the old 4000 CMOS logic is normally fins with no or very little decoupling. Just put a 100nF or so on the output of the regulator and all will be well.
 

Offline ogden

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Re: Sharing decoupling capacitors
« Reply #28 on: May 17, 2019, 11:01:27 pm »
Heh.. I would dare say size is a counter indication to competence (the Peter Principle).

Nah. Small companies have incompetent engineers as well, they just do not last long - either incompetent engineer in small company or small company riddled with incompetence. That's why you see mostly competent engineers in small companies :D
« Last Edit: May 17, 2019, 11:03:08 pm by ogden »
 

Offline T3sl4co1l

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Re: Sharing decoupling capacitors
« Reply #29 on: May 17, 2019, 11:24:07 pm »
Nah. Small companies have incompetent engineers as well, they just do not last long - either incompetent engineer in small company or small company riddled with incompetence. That's why you see mostly competent engineers in small companies :D

Yeah; to put more nuance on it, I would suppose you could plot competence vs. company size and get a scattered mess, where there is a large variance at the low end and a smaller variance at the high end, with the general trend overall as described.

Tim
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Offline OwO

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Re: Sharing decoupling capacitors
« Reply #30 on: May 18, 2019, 02:11:00 am »
How does the absolute distance come into this?
Distance between power and ground plane determines the impedance seen at a given point between the two planes that isn't very close to a decoupling cap. The simulation tool linked by schratterulrich should be able to show this.

Onchip decoupling is the reason chips still work at all considering the huge bondwire inductance and the interposer wire length (for BGAs), so usually it's not critical to get down to the last mm of distance between cap and pins, hence why caps at the bottom side of the board is just as good for high speed designs (Zynq) without needing a power/gnd plane pair.
« Last Edit: May 18, 2019, 02:12:44 am by OwO »
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Offline OM222OTopic starter

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Re: Sharing decoupling capacitors
« Reply #31 on: May 18, 2019, 04:17:31 am »
Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB:


they just went to town with ceramic caps for the VRM since the pick and place was going to take care of it.
 

Offline floobydust

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Re: Sharing decoupling capacitors
« Reply #32 on: May 18, 2019, 05:09:57 am »
Decoupling capacitors were explained in university, based on TTL gates switching and DIP packages and short PCB traces to a through-hole capacitor.
TTL totem-pole shoot-through current was the main issue, and based on total inductances of the capacitor, pcb traces, DIP package, around 0.01uF was enough to stop glitches on 5V rail. Using 0.1uF was 10x needed and afforded extra insurance for larger parts like SRAM and became common practice.

But on cell-phone modules +4V rail I see multiple staggered values like 10pF, 33pF, 100pF, 1nF, 10nF, 100uF on factory datasheets. TX currents to 1A on 800-1900MHz up, I guess the SRF of each decoupling capacitor needs to overlap.
iPhones are well engineered this way too, check some of their schematics.
 

Offline schratterulrich

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Re: Sharing decoupling capacitors
« Reply #33 on: May 18, 2019, 07:58:43 am »
For critical projects we don't use 100nF caps at every IC anymore in our company. Instead we use very thin core and prepreg material with a thickness of 50µm for every power rail. The disadvantage is that we usually need 12 to 16 layers. Then we place capacitor groups around the board evenly distributed. Due to the thin core material and the very low inductance of the resulting plane pairs the caps don't need to be placed ACAP to the ICs. The values of the capacitors have to be determined with a simulation.
We have very good experience with EMC and ESD with this approach.
Also the routing is easier especially because we need the space around the ICs mostly for series termination resistors.

Of course for boards with lower layer counts we still use conventional decoupling caps at every IC and I would strongly recommend them.
It is difficult to test your design for all conditions even if it works in the lab.
 

Offline rstofer

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Re: Sharing decoupling capacitors
« Reply #34 on: May 18, 2019, 04:24:02 pm »
also since you brought up I2C, I didn't use pull ups for the exact same reason (not enough space) and after checking with a scope, the edges couldn't be any more square even with the fastest mode. I'm assuming it's due to short traces which means pretty much no parasitics.

I2C pins are open collector or open drain.  Section 3.1.1 here:

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

What is providing the pull-up for your test?  Something is doing it and shouldn't be.
 

Online ataradov

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Re: Sharing decoupling capacitors
« Reply #35 on: May 18, 2019, 04:53:23 pm »
What is providing the pull-up for your test?  Something is doing it and shouldn't be.
He already replied - internal pull-ups of the MCU. And they do work fine for short traces in my experience too, even though they are typically an order of magnitude higher than recommended.
Alex
 

Offline T3sl4co1l

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Re: Sharing decoupling capacitors
« Reply #36 on: May 18, 2019, 08:22:58 pm »
How does the absolute distance come into this?
Distance between power and ground plane determines the impedance seen at a given point between the two planes that isn't very close to a decoupling cap. The simulation tool linked by schratterulrich should be able to show this.

Ah, but that's the third variable: distance!

Inductance is always proportional to a volume ratio length.  Or whatever it's called.  To get the resistance of a solid, you take resistivity and divide by (cross-sectional area divided by longitudinal length).  Same with inductance, where the area is that of the transmission line cross section (with a geometry factor of course), and the length is the length of the line.

If we consider the inductance of a via into a plane, we can look at the inductance of a cylindrical cavity resonator, where the height is very short (so we can ignore edge effects), the inner radius is the diameter of the via, and the outer diameter is an arbitrary boundary.  The boundary might be a wall of nearby vias (which again, for the power planes case, are vias to bypass caps), or the edge of the board (in which case the inductance acts in series with the plane capacitance, and we have a series resonance -- this is the lumped equivalent of the first standing wave mode between the planes), or to infinity if we wish to look at the asymptotic case.

We use a cylindrical model, because we're looking at waves propagating from the via radially.  Of course, if we have vias placed in this plane in arbitrary locations, their radial "fields of view" will overlap, and for example the inductance between two vias will be approximately the sum of both inductances, when outer diameter = distance/2, but there will be some mutual inductance between them as well (where outer diameter > distance/2), so we could draw a more detailed diagram accordingly.

When the problem is set up as such, and the integral is solved, we get a logarithmic result:
L = k * mu * h * ln(D/d)
(I forget exactly if there is a constant of proportionality there; it may be k = 1, and also mu = mu_r * mu_0 but we can just use mu_0 for PCB because mu_r = 1...)

Putting in typical values, we expect figures close to the usual via inductance figure itself, and since it varies logarithmically with D, we aren't so worried about how far away things are, beyond some point.  We do get some advantage when a capacitor can be placed at a distance less than h away from the via (on same layer), but if not (or when not required), the added inductance of the plane to other nodes is quite small.

Take for example mu = 1.257 nH/mm, h = 1mm, D = 20mm and d = 0.3mm.  The log is 4.2, so it's like having a 4.2mm tall via, and L = 5.3nH.  Not much, comparable to a few mm of trace length!

I would be quite happy doing this for an MCU, which might draw a rate of 100mA/5ns (say by toggling a full port of LEDs).  Times 5.3nH, this is a peak voltage (at internal VCC) of only 106mV, a few percent out of a 3.3V supply.  And indeed, I do this regularly, and the MCU has never shown aberrant behavior. :-+

We can also consider a ring of vias, or any arbitrary clustering of vias with an equivalent diameter of d, and apply this formula.  (Or use this formula in reverse to solve for the equivalent diameter of that pattern, given another calculation or measurement of the inductance.)  This of course demonstrates why multiple vias are valuable (a circle of vias of say d = 2mm in the same setting gives about half the inductance in the same case).

Regarding mutual inductances -- crafting a lumped equivalent of a distributed structure (following a transcendental function, at that) would be very tough, so if we need detail quite on that level, we might as well just break it up into a grid and approximate it that way; hence, the analysis program above, of course. :)

Tim
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Offline NorthGuy

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Re: Sharing decoupling capacitors
« Reply #37 on: May 19, 2019, 04:13:32 am »
Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB:

If you have millions of FETs simultaneously switching at tremendous speed, you do need lots of capacitors. And they have to be very fast and therefore small. Thus it's really hard to gather enough capacitance.
 

Offline DaJMasta

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Re: Sharing decoupling capacitors
« Reply #38 on: May 19, 2019, 07:43:14 am »
Tim if you want an example for overkill decoupling, look at the 2080 Ti kingpin PCB:

If you have millions of FETs simultaneously switching at tremendous speed, you do need lots of capacitors. And they have to be very fast and therefore small. Thus it's really hard to gather enough capacitance.

It's also a model that's advertised for overclocking, so they guild the lily with decoupling caps and VRM phases with the hopes that overdoing it will help keep things stable above normal clocks.  They know that people who are spending for the top card with the intention of overclocking will buy based on good results they hear about, so if they can go the extra mile in their design to overcome potential overclocking limitations with a dollar of extra caps and pick and place time, it's definitely in their interest.
 

Offline LukeW

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Re: Sharing decoupling capacitors
« Reply #39 on: May 19, 2019, 08:27:54 am »
A picture of your layout would be more significant than the schematic.

It's all about minimising the parasitic inductance, and getting those decoupling capacitors as close as possible to the loop on the IC where the current is actually going.

"Electromagnetic Compatibility Engineering" (H.W Ott) has a great treatment of decoupling capacitors.
 

Offline LukeW

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