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Sharing SRAM device in bettween two bus masters - how was it done back then?
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Yansi:
Hi!

Just as a mind exercise, I have kind of thought (to certain detail) how a composite video generators capable of displaying text may have been done in the past, in numerous 8-bit microcomputers.

The principle of generating video signal is rather simple: A text containing SRAM, character generator ROM and a couple of X any Y position counters, that generates pixels into lines and rows, reading the SRAM and CGROM sequentially.

What I do not understand and could not come up with a simple solution is, how could I share the SRAM device in between the precise periodic reading action of the video generator, while accessing the SRAM for R/W of text asynchronously from the main CPU?

I know that some 8-bit microcomputers had dedicated functionality to ease situations like this, but the question is, how would one solve this?

Supposed I have 8 pixels wide character on the display. That means that for at least every 8th pixel I need to read a character from the video SRAM. So for example having a line of 256 pixels (up to 32  characters per line) and while the video line is 64us (PAL), I need a pixel clock of 4MHz (because 256/64us = 4MHz). So every 2 microseconds I need to pull data from the SRAM.

How am I supposed to interface the SRAM to both the synchronous reading at 500kHz rate (4MHz/8pix wide chars), while being able to R/W access the SRAM from an external bus master, that operates at a completely asynchronous clock? Suppose I want to make an external peripheral for an 8-bit microcomputer, that would display text using composite video. So no modifications possible to the host system. It just provides its address and data buses, /WR and /RD signals.

Is there any obvious solution to it, that I have missed?

Please do not suggest using dual port SRAM. Or FPGA, or dedicated video chips. That is not defined as "back then" when  7400 TTL chips were the ducks guts and memory extremely expensive.

Just curious how things may have been done. 

Thank you for any tips.
Yansi:
So okay, maybe found one way to implement this easily enough, with maybe acceptable drawbacks:

Just give the CPU system higher priority. Whenever it wants an access, it gets it. In that case, pixel values displayed may be corrupted. That may or may not be an issue, can't tell how big.

However in this case, switching the 1K SRAM (32x32 chars) in between the CPU host system and the video HW may be done with just four interface ICs like 74244/74245.  (probably only 4 chips required).

BrianHG:

--- Quote from: Yansi on November 26, 2018, 10:56:21 pm ---So okay, maybe found one way to implement this easily enough, with maybe acceptable drawbacks:

Just give the CPU system higher priority. Whenever it wants an access, it gets it. In that case, pixel values displayed may be corrupted. That may or may not be an issue, can't tell how big.

However in this case, switching the 1K SRAM (32x32 chars) in between the CPU host system and the video HW may be done with just four interface ICs like 74244/74245.  (probably only 4 chips required).

--- End quote ---
You might also be able to use a 74LS/74HC574 to clock latch the data bus.
Jr460:
How about the CPU has lower priority and you use the wait line on the CPU who the video is reading the RAM.
Yansi:
BrianHG: That solution I have described needs bus switches, not bus registers.  574 is a register (octal DFF), 244 (245) is just tristate (bidirectional) switch.  :-//

Jr460: For example 8051 and compatible do not have any wait lines. Hence why I have written "I know that some 8-bit microcomputers had dedicated functionality to ease situations like this" - I think the 8080 system had the wait signal or sort of.

More interested in how that could be implemented without such signals?
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