(This is all non-serious shower thoughts, not an actual production project)
My best scope at home (HP 54600 series) is 100MHz analog bandwidth but only 20MSPS @ 8bits.
You can buy
~$5 ADCs that do 60MSPS @ 10bits (edit: woops 50MSPS, but close enough). I'm sure my first designs with it would have all sorts of problems, but it would be fun and I could throw some basic relay-switchable analog filters into the mix.
Triggering, signal averaging, etc: doesn't matter as long as I could continuously (without gaps!) stream all samples to something like a desktop computer or laptop. Then I can do everything in software on the powerful machine. In fact this would be a lot better than many USB scopes I have seen (which have abysmal sampling speeds if you can't tolerate gaps in your capture).
Getting the data from the ADC to a computer is hard?This is where my shower thoughts start to fall apart. How do I easily get high bandwidth digital data into a desktop computer?
60MHz @ 8bits is 480Mbit/s minimum, in reality the link will need to be faster.
Ethernet raw via discrete chips: Doesn't look as simple as a few discrete chips buffering samples into a pair of SRAMs and then spamming hardwired frames at an ethernet transformer. There is scrambling and negotiation needed (1000baseT requires one end to elect to be the master clock source, amongst other things). In practice you could probably skip a lot of the standards and use something like an ethernet switch chip to patch over the holes (eg retransmissions, collisions, some bits of autonegotiation) but I think it would still end up rather complex.
Ethernet raw with an FPGA: Spiritual and cost failure. If you use an FPGA I feel like you're already making a design similar to commercial oscilloscopes. I don't have much experience with FPGAs, but I presume a 1000baseT implementation would require the resources of a chip that costs a magnitude more than the ADC I link above.
Ethernet 1000baseT via an ethernet interface chip: All of the gigabit NIC chips seem to be built around PCIE as an interface. I'll keep digging to see if it's something you could feasibly cheat and use something simple with.
Ethernet 100baseT via an ethernet+network stack interface chip: These have much simpler interfaces like SPI and parallel. Sadly the highest I've seen (WIZNET-W5500) is claiming somewhere between 33MHz and 80MHz max theoretical SPI clock, so the actual analog sampling on the scope frontend is going to be well below 10MSPS
USB interface chips: UART USB bridges obviously won't do. Again PCIE might be the only interface option at these bitrates?
SBC computer or random allwinner SoC: Peripheral clocks are often a fraction of the core clock, but this might still allow 100MHz or so of digital data (more than 10MSPS of 8bit analog captures) to be ingested. Then stream it out via ethernet, PCIe or USB. Actually this sounds quite disappointing, especially since you'd probably have to do more than just a Linux userspace implementation of it to avoid timing issues (skipping incoming data).
Am I missing something here? Why is there such an imbalance in cost and complexity between the ADC chip itself and the ways of getting its data into a computer?