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Sigma Delta ADC Design
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iMo:
While watching the achievements in the Multislope design thread I've tried with a simple Sigma Delta ADC in hardware, no simulation this time :) ..

With UPduino v1 and the Lattice's "Simple Sigma Delta ADC Design" whitepaper I wired an 18bit ADC, with 22bit accumulator and 4 LPF_depth_bits I get 1 measurement in 2.8seconds. Internal FPGA's 24MHz RC oscillator is used.

Link to the SD ADC paper. You may download verilog source from that site too.

The FPGA's DDR input primitive for the input stream is used. The FPGA's LVDS comparator could be selected provided you can source the IO bank with 2.5V (UPduino is hardwired to 3.3V).

The max PWM frequency I can see is around 4MHz.

The schematics is pretty simple, see below. The 5V comes from a phone charger, 3.3V comes from BluePill (used as voltage regulator only).

UPduino and LM311 are put on a solderless breadboard. Serial in/out comes from the iCE40 FPGA via HC-05 into the PC.

Teraterm is used for logging data and communication with a built-in mcu, TimeLab for visualization of data.

No special voltage regulators or references are used.

The SD ADC's output data are from aprox 7600 to 262000 with the 10k 10t pot.

So far I get "5.5digits" where the last digit is jumping +/- 1 typically when the pot is wired to 3V3 - that is the ref voltage for the PWM as well, therefore the "stability" is expected.

When the guys finalize the multislope we may measure the INL and stability of this simple SD ADC..   :P

Update: updated the schematics and measurements.


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--- End code ---
iMo:
First measurement - a TL431 @2.5mA instead of the pot.
Kleinstein:
I think one of the problems of the simple circuit is that one directly gets the noise (including the 1/f part) and drift from the LM311. AFAIK there are not much noise specs on the comparator, but I am afraid the noise would not be very low, like what one would expect from a low noise op. The LM311 also has quite some bias current, that can be a factor.

The effective reference is the 3.3 V supply for the PWM signal - so a rather low level, that makes the noise rather important. There are probably better 3.3 V regulators than the blue pill  :-DD.
iMo:
The PWM would require a different approach - there will be a buffer made of a single gate (5 pin smd) powered by an LT1021B-5.
Also a canned 3.3V xtal oscillator, and PLL (there is one in the fpga) say 80MHz feeding the SD ADC clock.
Also the comparator will be different, sure :)
Then we need a better filters in the dsp chain as well. Etc. Etc.

PS: so far I've been messing with fp, after a "calibration" my UPduino is finally printing TL431's voltage in the new Volt :)

--- Quote ---2.54616
2.54617
2.54613
2.54600
2.54598
2.54581
2.54578
2.54578
2.54559
--- End quote ---

FYI - this is how the raw 18bit data (2x16b) is read out off the SDADC and then printed out as the voltage  :)

--- Quote ---: sdadc 700 io@ 701 io@ ; 
: sdf sdadc d>f ;
: sdvf f# 0.007069e f# 1.3e-5 sdf f* f+ f. ;
--- End quote ---

Wimberleytech:
Cute!
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