I am laying out an ADuM7701 isolated sigma-delta modulator ADC. This will run around 20MHz and I'm concerned about noise affecting my analog measurements.
I've attached photos of the schematic and my layout attempt. This will be a 6-8 layer PCB with both PWR and GND planes connected directly to their respective vias. Note that the analog side (left) is isolated from the digital side (right). The pads are test points for a scope probe tip to directly fit in. Some design rationale for the decoupling cap layout includes:
- I added multiple vias per 5V/GND to decrease loop inductance. I kept the opposing current vias (5V/GND) close together, and same current direction vias (GND/GND, 5V/5V) apart to reduce mutual inductance.
- The tracks from each ground pin to each decoupling cap ground provide a low inductance path from each PWR pin to GND pin for the IC.
I'm not sure if the 5V via placement (one at the pin, one at the decoupling cap) makes sense. The idea is related to this StackExchange thread which doesn't seem to have a consensus on via placement -
https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout.
Also, will the in-line test points affect my digital signal integrity at 20MHz? I may need pretty long trace lengths, I have source or termination impedance matching resistors on each digital line, and plan on doing impedance controlled routing.
Any criticism appreciated, thanks!