EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: cncjerry on March 21, 2019, 09:03:27 pm
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If I wanted to lower the slew rate of a transistor, basically limit it frequency response, what parameter would I modify, assuming this is so simple?
I'm trying to figure out what is going on where my spice model doesn't match the live circuit. Only thing I can figure is that the MC3346 NPN array is somehow not performing as expected.
Thanks
Jerry
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CJE and CJC, but you are just poking around in the dark fiddling with these. You should try to find the models for that device.
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Wimberleytech, thanks. I have the model for the RCA part, CA3046 and as expected the bandwidth is much higher than the live circuit (I don't see the rise time increase through the amp). I wanted to play with as you suggest CJE and CJC to see if by increasing them I can in effect better duplicate the live circuit. Adding 50pf just about anywhere will cause the problem I am seeing in the actual circuit.
I find it hard to believe the NPN array failed as well as it having such a high junction capacitance from the start. I mean it is always possible, as I've only ever seen these used in low frequency applications but then again, that would only be about 4 or 5 data points.
Thanks again,
Jerry
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Adding 50pf just about anywhere will cause the problem I am seeing in the actual circuit.
Yup, that seems a bit large. What is the circuit you are building/simulating?
I suggest that you simulate a single transistor and test for ft and see if it matches with the datasheet.