| Electronics > Projects, Designs, and Technical Stuff |
| Simple single-supply, negative ramp/sawtooth generator idea? |
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| soldar:
--- Quote from: ebastler on November 09, 2019, 09:47:17 pm --- From an FPGA, I would like to drive a simple negative sawtooth output: With approx. 3 kHz repetition rate, set the output "high" (rise time up to 1µs), then let it fall reasonably linearly to the "low" level (for approx. 300µs). "Resonably linear" means within a couple %, so no high precision requirements, but exponential capacitor charge/discharge curves won't be good enough. --- End quote --- A (constant) current source will charge a capacitor linearly. If you add a diac or UJT or similar circuit it will discharge the capacitor suddenly when the threshold voltage is reached. As has already been said, you can modify a 555 astable oscillator so that the capacitor charges through a constant current source. |
| SiliconWizard:
A simple and low-power variant can be built around a JFET (see attached). V1, V2 and S1 are a simple model of a digital I/O driven as '1' (for 1µs) or as Hi-Z (for the rest of the period) alternately, so it's just a small capacitor, a resistor and a common JFET. You will probably need to buffer the output though (with an opamp for instance) depending on what it's going to drive, since loading the output can distort the signal significantly. You can also play with the capacitor value vs. the resistor value (which defines the constant current for the discharge). |
| ebastler:
--- Quote from: SiliconWizard on November 10, 2019, 11:17:52 pm ---A simple and low-power variant can be built around a JFET (see attached). V1, V2 and S1 are a simple model of a digital I/O driven as '1' (for 1µs) or as Hi-Z (for the rest of the period) alternately, so it's just a small capacitor, a resistor and a common JFET. You will probably need to buffer the output though (with an opamp for instance) depending on what it's going to drive, since loading the output can distort the signal significantly. You can also play with the capacitor value vs. the resistor value (which defines the constant current for the discharge). --- End quote --- Thank you -- that's a nice one! Who would have thought that there is so much to be learned (for me) from that simple application! Thanks for pointing out the potential need for an output buffer. I would like to drive a 50 Ohm cable; some loss of signal level would be OK, but no major distortion of the output. Of course, the need to buffer the output applies to the "single NPN transistor" or PWM solutions too. So now all that remains to be done is to select the solution I actually want to put on my PCB... |
| magic:
At this point I might as well shill for my favorite obscure component: the depletion mode MOSFET ;) But there is a problem with all kinds of FETs and not without reason did SiliconWizard cleverly conceal what happens when the output gets close to ground ;D A bipolar sink could go almost all the way down. Not that you care, so whatever. |
| SiliconWizard:
If you really want to do without an opamp for buffering the output for some reason, you can buffer it with just an appropriate MOSFET as a follower (appropriate meaning: must have a low enough VGS(th).) Attached an example - the BSS123 works as an example here, but you can find many other N-ch MOSFETs with a low(er) VGS(th). The output signal will be shifted down. And of course, as magic hinted above, the key here is to choose the discharge current so that the output voltage always stays well above ground (all the more if you're buffering the output!), which is no problem here, since you mentioned that your requirement was a 1Vpp signal, so this circuit is designed assuming you don't care about the exact min and max values as long as the p-p amplitude is sufficient. Design with a comfortable margin, because there's a relatively wide dispersion in the constant current you'll get depending on the JFET. |
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