Well, lets face it -- my analog design skills are marginal.

So I could use some help...
From an FPGA, I would like to drive a simple negative sawtooth output: With approx. 3 kHz repetition rate, set the output "high" (rise time up to 1µs), then let it fall reasonably linearly to the "low" level (for approx. 300µs). "Resonably linear" means within a couple %, so no high precision requirements, but exponential capacitor charge/discharge curves won't be good enough.
I have a 3.3V supply available. To drive/trigger the ramps, I can provide one or two (complementary?) digital signals with whatever duty cycles makes sense, toggling them between 3.3V and 0V, or high-Z if that helps. The output does not have to operate rail-to-rail (0V to 3.3V), but at least 1V
p-p output amplitude would be desirable.
There must be a simple solution to this, using an op-amp or two, or an NE555 -- but I have not found any "cookbook" solutions, and can't figure out anything simple myself. Any ideas or pointers are much appreciated!