Simple Sinusoidal Oscillators

[mawyatt]

Edited the previous post earlier and if you look at the image, this is the correct equation which was captured from here

V_"ee" > V_t \left( 2 * (R + sqrt\(R^2 + Z * R))/{Z} +  \ln (\left(V_"ee" - V_"be")/(R * I_s)\right)\right)

http://asciimath.org

https://math.meta.stackexchange.com/questions/5020/mathjax-basic-tutorial-and-quick-reference

Used the link and code ReGeorge posted and did some editing to get the equation correct using the syntax you used.

\[V_{ee} > V_t \left( 2\cdot\left(\frac{R + \sqrt{R^2 + Z \cdot R}} {Z}\right) + \ln\left(\frac{V_{ee} - V_{be}} {R\cdot I_s}\right)\right)\]

Thanks for the help 


Best,

[mawyatt]

As a side note, my Peltz-Wyatt oscillates just fine starting from anything above 0.7-0.8V but the amplitude is very small.  For example at 0.9V the sound card measures -100dBVrms, so about 25uVpp, and the DC level is very jumpy, so I can not use the oscilloscope in averaging mode.  Not sure if the signal jumps because of shot noises or because of the breadboard contacts, I suspect it's not the breadboard.  The attached spectrum is for Vcc = 0.9V, barely visible above the noise floor.

Regarding the signal level, yes that's small, if you can't use a larger Vee supply voltage then try using a smaller Ree which will increase the transistor transconductance gain which is linear with collector emitter current. This will cause the dynamic signal swing to go further into the forward bias CB junction during the signal +- peaks such that the integral over the waveform cycle is unity gain for the positive feedback loop. In other words, the waveform will experience more dynamic gain around the center and more gain compression at the peaks such that the cycle by cycle average is unity.

This more dynamic gain around the center and more gain compression at the peaks gets into an area of advanced research that was going on awhile back before we retired. This was related to low noise tuned/filtered amplifier and oscillator design that was completely opposed to conventional thinking, where ultra linearity was "believed" to produce the lowest noise results. The new idea was to slam the active element(s) into gain compression at cutoff and saturation where the incremental gain is almost zero, then allow large gain during transition between these compression regions, the less time spent in the "gain" transition area the lower the average overall noise per cycle.

The idea was that during the high compression regions the active element(s) produce almost no noise since they are effectively highly compressed gain-wise, and only produce noise when in gain transition between the gain compression regions. BTW this was not the usual limiting type designs for high efficiency, but utilizing this limiting "gain compression" property to achieve low overall average noise per cycle. Recall this research was going on at MIT, Berkeley and/or Stanford.

Anyway, a topic for another thread that others might want to investigate (can't recall much other than having dinner/drinks some time ago with one of the key early researchers involved), but makes one consider if the Peltz Oscillator is "driven" harder by higher device bias currents if the overall output noise improves??

Best,

[Kleinstein]

For most simple uses the noise is not that relevant. The gain compression has however also a positive effect on the amplitude stability. The petz oscillator tends to produce a rather stable amplitude. With the 1 transistor Pierce  or Collpitz oscillators one can run into the problem that the amplitude gets anstable and worst cost one gets an extra AM modulation for free.

There are 2 effects stabilizing the amplitude: the gain saturation of the LTP when the amplitude is larger than some 50 mV and than the clamping action of the BE / BC junctions when the amplitude exceeds some 600 mV.  So the amplitude and main active mechanism can effect the distortion. Chances are the clamping action would produce more pronounced distortion.

[mawyatt]

Agree the amplitude stability under "heavy" limiting is good.

The clamping or limiting action of the transistors is in the CB junctions of each transistor, Q2 for the + waveform peak and Q1 for the - waveform peak. However it's not limiting in the conventional sense, it's causing the overall cycle by cycle gain to be unity, where the mid-waveform gain is higher than 1 and the +- peaks compress to below 1.

This isn't the conventional type thinking of "gain", but more of a "gain" distributed across the entire cycle where the cycle-average must be unity. So the CB junctions actually "come into play" well before the usual 0.6 diode effect at small transistor transconductance and can be estimated as the usual Diode Equation.

If you check the first post there's link to the Peltz Oscillator we provided and it shows adding series R to the base of Q1 and Q2 to increase the output amplitude. What's interesting is that adding a resistor in the signal path (that doesn't change the bias) causes a signal output increase, contrary to intuition. This is because the added resistor is affecting the cycle by cycle loop gain at the waveform +- peaks where the incremental gain must dive below 1 so the cycle average is unity, and thus the waveform is larger in amplitude.

Anyway, it's fun to build one of these simple Peltz Oscillators and watch the waveform behavior under variations in bias and looking at oscillator start-up conditions (why we posed the equation for startup minimum Vee). At low bias current levels the transistor transconductance is just enough to overcome the coil and capacitor losses and the loss due to Re (so cycle gain is almost unity everywhere), as the bias increases (larger Vee), so does the transconductance (linear with current). You can witness the CB junction conduction that begin to change the cycle gain at the peaks by softly introducing a dynamic loss impedance well before the usual ~0.6 volt differential.

Best, 

[RoGeorge]

Made a detour through the software land and when I wanted to make a few more test I've read this thread again, only to notice I was on a wrong path.  ADI page was pointing at the BC junctions in parallel with the LC tank, and how they will act as limiters, and that remark fooled me into assuming the BC forward polarized are the main mechanism of limiting/distorting the signal.

There are 2 effects stabilizing the amplitude: the gain saturation of the LTP when the amplitude is larger than some 50 mV and than the clamping action of the BE / BC junctions when the amplitude exceeds some 600 mV.

Noticed the similar reply before, already familiar with the idea highlighted there, yet I've somehow failed to register or to consider that.    In fact, when I've read your message about BE pair clamping some pages ago I assumed that's a typo, and that you meant the anti-parallel BC diodes clamping, sorry.

Indeed the input range for good linearity in a BJT pair is way lower than the 0.6V clamping caused by the forward polarized BC junctions in this particular arrangement of the LC tank.  And if it were to try to extend the input range where the response of the BJT pair is still linear (since I was seeking to lower the distortions), I should have added a resistor in each of the emitters instead of increasing the common resistor.

Talking about Fig.9 at page 10 here:  https://engineering.purdue.edu/wcchew/ece255s18/ece%20255%20s18%20latex%20pdf%20files/ece255Lecture_19_Mar29_Diff_Amp_Cont.pdf

Have to redo, but at least now I know how to sample at 24bits/96kHz from Python. 

[mawyatt]

Indeed the input range for good linearity in a BJT pair is way lower than the 0.6V clamping caused by the forward polarized BC junctions in this particular arrangement of the LC tank.  And if it were to try to extend the input range where the response of the BJT pair is still linear (since I was seeking to lower the distortions), I should have added a resistor in each of the emitters instead of increasing the common resistor.

Talking about Fig.9 at page 10 here:  https://engineering.purdue.edu/wcchew/ece255s18/ece%20255%20s18%20latex%20pdf%20files/ece255Lecture_19_Mar29_Diff_Amp_Cont.pdf

Have to redo, but at least now I know how to sample at 24bits/96kHz from Python. 

Don't think of the BC junction as a limiter, better to think of this as a means to extract energy from the LC network on a per cycle basis and create a net energy added/lost ratio per cycle which is exactly unity. Adding separate emitter resistors for Q1 and Q2 linearizes the transconductance but at the expense of reduced loop gain (lower transconductance) which require higher device bias currents, whereas adding resistors to the base of Q1 and Q2 allow more signal swing and less energy lose per cycle to the BC junctions, but have less effect on Q1 and Q2 transconductance.

For the lower harmonic distortion, then one wants to balance the transconductance linearization with marginal energy lost to the BC junctions, however this may not yield the best overall SNR for the fundamental.

Another side thought you could create a similar oscillator with a pair of NMOS devices, the output voltage should be much higher but won't have the benefit of the energy loss to the bipolar BC junction unless the gate has some sort of a protection diode built-in.

Anyway, fun little circuit to play around and experiment with!!

Keep experimenting 

Best, 

[RoGeorge]

In terms of energy, what bothers in respect to low distortions is the fact that energy is extracted at faster rates in the regions around the voltage peaks on the LC, which means altering the natural LC swing strongly around the peaks, which means distortions.

Another thing that bothers me is that the voltage at the non grounded end of the LC tank, V(out), is swinging above and below the GND.



Because the two BC junctions are directly connected to the LC tank (in anti-parallel), this implies at any time one transistor will have its CB junction forward-biased (one transistor at each half of an oscillation), so each transistor will be saturated, alternatively, for half of the period.

For this reason I'm tempted to say this circuit only looks like a differential BJT pair, but shouldn't be looked as a linear BJT pair.

[mawyatt]

Yes it is a simple diff pair since the total negative emitter currents thru the emitter resistor are split between Q1 and Q2 but not exactly equally. Q1 emitter current only peaks below that of Q2 because its base never goes above ground. Plot the two emitter currents and you will see this, note how the tend to equalize as the emitter resistor gets larger along with the negative supply, better approximating an emitter current source. With an high emitter current source impedance Q1 and Q2 emitter current equalize. When the total emitter currents are just enough to sustain oscillations with a high emitter source impedance Q1 and Q2 currents very close and just a hint of flat topping at the peaks, and the output voltage waveform looks like a nice sinusoid!!


Best,

[RoGeorge]

Plot the two emitter currents

Followed your advice, thank you, plotted that and been surprised and intrigued, so plotted all trying to understand better.



Next simulation is after replacing R with a CCS.



In each of the two simulations above:

- First plotting panel is with Vbe and Ie for each Q1 and Q2.
- Second panel is for voltage and currents through L and C.
- Added a series Rsense to help detect when energy is pushed or pulled out from the LC tank, and plotting that in the third plotting panel.  Magenta is power on Rsense (so proportional with energy transfer with the LC tank, and the signum of the red plot I(Rsense) indicates the direction of the energy transfer.  The right hand Y axis in the 3rd panel (indicating nW should be read as uW, because Rsense is 0.001 Ohm.

Plots were already too crowded to step through different R (or I).  Instead, looking at the different regimes the oscillator goes through from start to stable oscillations.  (assuming a period of a lower amplitude - seen here during start - will look about the same as a stable oscillation in a schematic with a bigger R or a lower I)

To ease the comparison of all plots at once between the two simulations, made an animated gif and stored it outside of EEVblog because the forum turns off any animations inside pictures attached here:



TL;DR  There's a lot of things happening there!   
Need to identify and decode each functioning regime.

[mawyatt]

Here's a plot showing Q1 and Q2 Emitter currents and the Output Voltage V(n002). This is with a bias current with some rounding at the +-peaks, and you can see the sinusoidal output voltage. The second plot shows with a much smaller emitter resistor (510) and Vee (0.9V), note how Q2 emitter current is much larger on the + Output Voltage swing since Q2 Base goes above Ground pulling the emitter voltage shown as V(n006) higher.

Would be interesting to see which of the bias cases produces the best SNR of the fundamental, the second case suffers from the larger peak emitter current of Q2 doesn't contribute to the output signal since it flows around the LC network.

Note we used a startup current source to kick start the simulation and achieve a stable output with less time in both cases.

Best,

[Seekonk]

Oscillators aren't any fun unless you put a lamp in them.

I had to build a calibrator for a product that had to trip somewhere from 20-100mv AC or DC. Exactly the same RMS value for both and of course it had to be adjustable. Did I say CHEAP. It used line AC and a DC source from that. I remembered seeing something in Electronics Design possibly as far back as the 70' that used a small lamp in a bridge. Line voltage could vary from 100V to 135 and it stayed spot on. Flip the switch and feed it DC and it was the same voltage.

[RoGeorge]

Would be interesting to see which of the bias cases produces the best SNR of the fundamental

If that is only to check if an amplifier is less noisy when driven into saturation, any amplifier should be so, if we think of noise as an input signal that would be amplified by the DUT amplifier.  The Vout vs Vin plot looks linear only at small signal.  For a bigger signal the plot shape looks like an S, and its slope (slope = DUT amplification) is big near zero and with no amplification at the ends of the S shape.

Considering the signal + noise input as a small noise added on top of a big signal, then the big signal will put the amplifier in saturation and will act like a "bias" on the Vout vs Vin plot.  When saturated the amplification is small for everybody, including for noise.  A large swing of the useful signal will keep our amplifier mostly in its saturation regions, so the input noise won't be amplified either, and thus on average the saturated amplifier will show less noise at its output.

In real life, this saturation and how it affect smaller signals can be observed as "blinding" (by a strong light source, or by a strong noise, etc.), when we can not see the rest of the image details because our senses were driven into saturation by the very strong "blinding" signal.

I think the noise is "lowered" in a saturated amplifier just like the details are lost when blinded.
The DUT doesn't see the noise any more because the DUT is blinded by the useful signal. 


If the F₀/noise ration is needed for something else, then LTspice might help, but I think this requires special models that includes noise.

Didn't play much with it, but LTspice has ".noise" type of analysis.  There are also ".four" and ".meas" SPICE directives that can write the results in the log file, and they could be used in combination with a ".step param".

The idea is to run two simulations:
- one for ".noise" with ".step param R1", and a ".meas" to get a RMS noise value for each .step
- one for ".tran" with the same ".step param R1", and a ".four" to get the amplitude of F₀

Then grab the data from the .log files (either manually, or with a script if the number of steps for R1 is very big) and calculate A²(F₀)/Noise_RMS for each step.

On a second thought, I don't think the ".noise" simulation will include the "blinding" caused by a large signal, just like an ".ac" type of simulation doesn't include large signal behavior. 


Maybe just adding a noise source somewhere in the oscillator would be easier.  Then run a normal ".tran" with ".step param R1", and then postprocess the result with a FFT to compute S/N ration considering only F₀, as requested.  On all these, overlap the noise from ".noise" at each R1 to include the internal noise of the circuit.  Probably not very accurate, but better than nothing.  (Not accurate because at large signal, the gain of the amplifier changes with the instantaneous amplitude of the signal, while in .noise the gain is considered constant no matter the amplitude.)
 


Side note, a ".noise" with ".step param R1" for the Peltz oscillator will also show the frequency response of the circuit, just like one can measure the frequency response of an RF amplifier using a noise source and a spectrum analyzer. 

[mawyatt]

Nice plots!! They show the effective oscillator "Q" growing as the bias is increased and reducing the effective bandwidth, however most SPICE types are linear noise analysis, so they don't take into account the non-linear circuit nature (Cadence has a non-linear noise analysis, but this is high end very costly simulation software) and it's effect on the overall noise performance.

Regarding the noise sources and device linearity.  One thing that occurs is that with heavy non-linearity various sources of noise get modulated into the signal of interest, this is why close-in phase noise wrapped around the signal appears. Much of this is from 1/f^n type noise from the active device(s), power supply rails, bias networks and so on, and this can corrupt things.

Because of this non-linear noise modulation effect, the reduced noise from the active device(s) in saturation and/or cutoff can be sacrificed to the modulated noise causes by the saturation/cutoff,  that's why we said "Would be interesting to see which of the bias cases produces the best SNR of the fundamental"

Way back in the old days many seasoned engineers believed that the lowest noise higher frequency oscillators were built with 3/5 compound semiconductors (GaAs for example), we proved we good outperform any of these noise-wise with a silicon based design using the same resonators because of the much lower 1/f^n noise the silicon device possessed.

Anyway, nice work and keep it up

Best,

[RoGeorge]

About that plot, thank you, I've noticed later something intriguing.  Not only that a higher current will ruin the Q, but a higher current will also shift (lowers) the resonant frequency. 

At first I've suspected that the frequency shift might be caused by parasitic capacitance in the transistors, but it even happens in my 3.5kHz audio oscillator, where C is 220nF, a huge value in comparison with any parasitic capacitance in a BJT.

Regarding the noise sources and device linearity.  One thing that occurs is that with heavy non-linearity various sources of noise get modulated into the signal of interest, this is why close-in phase noise wrapped around the signal appears. Much of this is from 1/f^n type noise from the active device(s), power supply rails, bias networks and so on, and this can corrupt things.

Because of this non-linear noise modulation effect, the reduced noise from the active device(s) in saturation and/or cutoff can be sacrificed to the modulated noise causes by the saturation/cutoff,  that's why we said "Would be interesting to see which of the bias cases produces the best SNR of the fundamental"

Wow, very clean explanation of how (amplitude) noise can turn into phase-noise because of non-linearities, thank you!

Also, had to google close-in phase noise to find if that's a dedicated term.
Google doesn't know very much about that, but had the luck to bump into a couple of papers that defined the term, one of which was this:

“Close-in” is defined at small offset frequencies, where the phase noise spectrum does not have a 1/f² shape. The analysis of phase noise at these frequencies is usually more complicated than that of the far-out phase noise mainly because close-in phase noise is, by definition, affected by low-frequency colored noise, such as generation/recombination noise and 1⁄f noise.

Source:  Close-in phase noise in electrical oscillators  DOI: 10.1.1.119.8656


In case your bias vs SNR to fundamental question was in regard to phase noise, then I'll expect that a lower I_tail will get a lower phase noise:
- first, because higher bias lowers the Q of the circuit, and a lower Q oscillator is easier to perturb than a higher Q oscillator, at high Q a resonator will want to stay in its narrow band, and oscillate there at higher amplitudes, thus harder to be perturbed by a given noise.
- second, because high bias current will produce oscillations with an amplitude big enough to enter into limitation, which means higher non-linearities, so even more noise will turn into phase noise by modulation on non-linearities.


So far I've only simulate (last week), and did some measurements now on that sloppy breadboard built:



- the frequency goes from about 3500 Hz (low current) to 2700 Hz (max current) then it stops
- the skirt of the peaks seems to widen while increasing the current, but it's hard to measure precisely with how much
- another observation is the 50Hz mains AM modulation becomes more visible at high current, which might mean that the oscillator is more sensitive to noises (assuming the induced mains hum is about the same, but this assumption might be wrong)

The attached spectrum is for about 1 minute of averaging, with two measurements overlapped:  red trace is for (potentiometer) R1=2k4 and green for R1=5k, osc powered at 5V from 4xAAA NiMH.  The 50Hz is from the breadboard wires.  For less than 2k4 the osc stops.

Looks like more current will produce more phase noise, and will also lower the oscillation frequency in a Peltz oscillator.  I'm curious if at higher frequencies would happen the same.

Did you happen to have any measurements about the phase noise?

[mawyatt]

In relation to the network "Q" and phase noise, this usually involves Leeson's Equation which shows Phase Noise follows 1/Q^2.

We have not made any PN measurements.

One explanation of the added 50Hz around the "carrier" is with the higher bias and increased non-linearity, the modulating function has greater "gain" and converting the lower frequency mains up to and around the "carrier" just as if it were low frequency "noise" and appearing as Phase Noise.

On the lowering of frequency, this may be due to the heavy forward bias CB junctions on the +- current peaks. This condition produces a large charge storage in the junction which "looks" like a heavy capacitance occurring at the +- peaks. A through detailed non-linear analysis might shed some light and may even show a oscillation dependency on the loop transconductance.

Best,

[moffy]

I built my own Peltz oscillator with 9mH/2uF and got a neat 1.6kHz sine from 1.5v with 10k Re. Then I thought the Peltz oscillator would make a simple AM modulator, so I simulated the following, makes a fairly decent AM modulator.

[moffy]

I might be the only one interested, but I have improved the Peltz oscillator AM modulator by damping the Q of the resonant LC and injecting the modulating current into the emitters of the differential pair. This gave a much greater depth of modulation, and makes it easier to modulate the amplitude.
Included is:
1. A picture of the simulated circuit.
2. A picture of the simulated output, with the green trace the point between L2 and collector of Q1. The blue trace is the output at the junction of C2 and R2.

[RoGeorge]

I might be the only one interested

I'm all ears. 
Did by any chance tested it in practice?  Does it works OK?

Asking because I've copied last Sunday this AM modulator



and it worked very bad.

My LC is a former AM ferrite rod antenna from a pocket radio, measured Q=55.  Some waveforms here, captured with the 10x oscilloscope probe connected to a second winding of 6 turns on the other end of the bar (the main L has 69 turns):  https://www.eevblog.com/forum/rf-microwave/how-can-i-improve-this-cheap-am-transmitter/msg4807103/#msg4807103

Next day I've tried changing the PSF, then stripped the schematic to a minimalist Peltz osc, and still doesn't look good.  In simulation works much better, so I'm curious if yours worked in practice as good as in simulation.

[T3sl4co1l]

Did you try fixing the base bias?  The unbalanced resistance to both sides I mean, 100k extra on the left side should run it pretty low.  Maybe add a 10k to the right side (cap bypassed to GND) and change the 100k to 10k.

It will always and necessarily run out of amplitude at low current; stable limit cycles require some minimum transconductance.  Conversely, at high amplitude, Ccb and Cbe voltage modulation will dominate the FM aspect I think.  I suppose feedback could be buffered (run it through an emitter follower? or maybe better yet, JFET source follower?) to help isolate Cbe, which should be the bigger effect.  Ccb can be dealt with by using smaller transistors (MPSH10?) and higher supply voltage (more specifically: lower amplitude in relation to supply).

Tim

[RoGeorge]

Did you try fixing the base bias?

Yes, I've tried changing the bias at first.  Sorry that I've wrote "PSF", that's the Romanian abbreviation for DC bias (PSF = Punctul Static de Functionare).

Tried many types of BJT's, too, they perform about the same (700kHz).  Hope to make more tests this weekend.  For now I'm tempted to give up that schematic, and use instead any other known working MW AM modulator usually used by hams.