Each output buffer its its own thing so you can chain together as many as you want to get the bus width you want. But do take care that they can run from the same clock, its quite common on FPGAs to have them run from a few different clock buses. Its best to just try synthesizing what you want and see if the compiler lets you place the stuff you want on the pins you want. This is always a good practice before making a PCB, if the compiler says its ok then it is ok.
Using DDR might also be attractive since it effectively doubles your speed, but this does make timing and routing a lot more stringent, so your choice if you want to take that risk. Usually FPGAs will have groups of DDR pins that have particularly well matched timings