Author Topic: Single ended Fpga To Fpga bus safe speed?  (Read 1972 times)

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Offline pacmannTopic starter

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Single ended Fpga To Fpga bus safe speed?
« on: August 01, 2021, 11:44:59 am »
I want to have a high speed bus between 2 Spartan 6 Fpgas. Whats a safe data clock speed I can use for the bus if single ended? They will be on the same circuit board 10cm away from each other and the tracks are going to be length matched.
 

Offline pacmannTopic starter

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #1 on: August 01, 2021, 11:51:37 am »
Also, I planned a single ended bus 32 bit wide. Is more bandwidth possible with a differential bus 16 bit wide? Is higher speed possible using the same pins but using differential pairs?
 

Offline dmendesf

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #2 on: August 01, 2021, 12:56:19 pm »
Yes, you can have a faster bus with differential signals. If you used a spartan 6 with high speed transceivers (and connected the right pins the right way with the right impedance...) You could have a few GBps per pair of pins. With common spartan 6 if you connect differential pairs correctly then you can use ISERDES and OSERDES to achieve a few hundred bps per pair of pins.
 
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Offline Bassman59

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #3 on: August 01, 2021, 11:17:44 pm »
I want to have a high speed bus between 2 Spartan 6 Fpgas. Whats a safe data clock speed I can use for the bus if single ended? They will be on the same circuit board 10cm away from each other and the tracks are going to be length matched.

We used to do parallel PCI at 133 MHz with 64-bit buses across VME boards, with proper line length matching and line impedance and minding the routing rules about jumping layers. So that's a good data point.

Spartan 6 doesn't have gigabit-rate SERDES but you should be able to run the serial differential traces at their top rated speed across 10 cm of board. Again, mind the impedance and the routing.
 
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Offline dmendesf

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #4 on: August 02, 2021, 12:54:08 am »

Spartan 6 doesn't have gigabit-rate SERDES but you should be able to run the serial differential traces at their top rated speed across 10 cm of board. Again, mind the impedance and the routing.

Spartan-6 LXT has gigabit-rate SERDES.
 
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Offline Bassman59

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #5 on: August 02, 2021, 04:33:19 am »

Spartan 6 doesn't have gigabit-rate SERDES but you should be able to run the serial differential traces at their top rated speed across 10 cm of board. Again, mind the impedance and the routing.

Spartan-6 LXT has gigabit-rate SERDES.

Ah, yes, indeed ... and it's been ages since I looked at the Spartan-6 devices. The world has moved on.
 

Offline pacmannTopic starter

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #6 on: August 02, 2021, 09:24:51 am »
Thanks all!
Yes, you can have a faster bus with differential signals. If you used a spartan 6 with high speed transceivers (and connected the right pins the right way with the right impedance...) You could have a few GBps per pair of pins. With common spartan 6 if you connect differential pairs correctly then you can use ISERDES and OSERDES to achieve a few hundred bps per pair of pins.
It looks like only only Spartan6 parts ending in T have high speed transceivers. Gigabit Serdes looks promising.


Spartan 6 doesn't have gigabit-rate SERDES but you should be able to run the serial differential traces at their top rated speed across 10 cm of board. Again, mind the impedance and the routing.

Spartan-6 LXT has gigabit-rate SERDES.

Ah, yes, indeed ... and it's been ages since I looked at the Spartan-6 devices. The world has moved on.
Is there a reason to move on from Spartan 6 in new designs? Looks like it is still supported and cheaper compared to the Spartan 7.
 

Offline pacmannTopic starter

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #7 on: August 02, 2021, 10:00:20 am »
From the Spartan 6 data sheet.
Quote
ISERDES2 Overview
Each IOB contains an input deserializer block that can be instantiated in a design by using the ISERDES2 primitive. ISERDES2 allows serial-to-parallel conversion with SerDes ratios of 1:2, 1:3, and 1:4. The SerDes ratio is the ratio between the high speed I/O clock that is capturing data, and the slower internal global clock used for processing the parallel data. For example, with a single-rate I/O clock running at 500 MHz to receive data at 500 Mb/s, the ISERDES2 transfers four bits of data at one quarter of the rate (125 MHz) to the FPGA logic.

  • Does this mean each differential pair can have a rate of 500 Mb/s in the example?
  • If I want lots of bandwidth can I use 8 differential pairs and each one of those differential pairs uses a 1:4 ratio for 4 Gb/s total bandwidth assuming -1 speed grade?
  • Do I have to worry about BUFPLL limitation or this will only use 1 BUFPLL because all the Serdes for the bus are using the same clock?

« Last Edit: August 02, 2021, 10:16:04 am by pacmann »
 

Online Berni

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #8 on: August 02, 2021, 10:44:52 am »
Each output buffer its its own thing so you can chain together as many as you want to get the bus width you want. But do take care that they can run from the same clock, its quite common on FPGAs to have them run from a few different clock buses. Its best to just try synthesizing what you want and see if the compiler lets you place the stuff you want on the pins you want. This is always a good practice before making a PCB, if the compiler says its ok then it is ok.

Using DDR might also be attractive since it effectively doubles your speed, but this does make timing and routing a lot more stringent, so your choice if you want to take that risk. Usually FPGAs will have groups of DDR pins that have particularly well matched timings
 
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Offline dmendesf

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #9 on: August 02, 2021, 01:08:46 pm »

  • Does this mean each differential pair can have a rate of 500 Mb/s in the example?

Yes. Mind that's an unidirecional channel.

  • If I want lots of bandwidth can I use 8 differential pairs and each one of those differential pairs uses a 1:4 ratio for 4 Gb/s total bandwidth assuming -1 speed grade?

Yes, but matching them can have some issues as another person said. It's best practice to try to sintetize your design first before doing your layout.

  • Do I have to worry about BUFPLL limitation or this will only use 1 BUFPLL because all the Serdes for the bus are using the same clock?

I don't remember the implementation details so can't help you here.
 
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Offline pacmannTopic starter

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #10 on: August 06, 2021, 07:34:02 am »

  • Does this mean each differential pair can have a rate of 500 Mb/s in the example?

Yes. Mind that's an unidirecional channel.

  • If I want lots of bandwidth can I use 8 differential pairs and each one of those differential pairs uses a 1:4 ratio for 4 Gb/s total bandwidth assuming -1 speed grade?

Yes, but matching them can have some issues as another person said. It's best practice to try to sintetize your design first before doing your layout.

  • Do I have to worry about BUFPLL limitation or this will only use 1 BUFPLL because all the Serdes for the bus are using the same clock?

I don't remember the implementation details so can't help you here.
Each output buffer its its own thing so you can chain together as many as you want to get the bus width you want. But do take care that they can run from the same clock, its quite common on FPGAs to have them run from a few different clock buses. Its best to just try synthesizing what you want and see if the compiler lets you place the stuff you want on the pins you want. This is always a good practice before making a PCB, if the compiler says its ok then it is ok.

Using DDR might also be attractive since it effectively doubles your speed, but this does make timing and routing a lot more stringent, so your choice if you want to take that risk. Usually FPGAs will have groups of DDR pins that have particularly well matched timings
Thanks!
 

Offline pacmannTopic starter

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Re: Single ended Fpga To Fpga bus safe speed?
« Reply #11 on: August 10, 2021, 10:02:20 am »
Using DDR might also be attractive since it effectively doubles your speed, but this does make timing and routing a lot more stringent, so your choice if you want to take that risk. Usually FPGAs will have groups of DDR pins that have particularly well matched timings



Im a little confused about the data sheet. The SDR and DDR Serdes bandwidths are the same values in the chart. Does this mean the max Serdes clock speed will be 950 Mb/s for a speed grade -2 for example, but the data speed will be 1.9 Gb/s if using DDR Serdes?
 


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