Slew rate control in high speed LVDS signals

[EEEnthusiast]

Hi
I need some method to be able to control the slew rate of LVDS signals with rates from 10MHz to 1GHz. The slew rate has to be variable from 0.1V/ns to 10V/ns in fine steps of 0.1V/ns.
The step size need not be precise but of that order. I have looked at FPGAs with programmable slew rate, but they offer 2 or 3 rates. Not very controllable fine steps.

Any clue how this can be done?

[Terry Bites]

I'm not sure if this is a useful response.

You would usually achieve slew control using a transconductance stage with a fixed capacitive shunt load.
This limits the charging current available to the capacitor but not it's final voltage.
Its just a voltage controlled integrator at heart. 
You'll need a very fast and OTA or VCCS for this to work. 

For a serious test instrument build, there is another way: Use high speed ADC(s) and DAC(s) back to back and control the output rise and fall times by changing the input to output clock ratio.
A demanding high bucks build with RF Voodo required.

[T3sl4co1l]

Signal level is low enough that you can probably get away with a varactor tuned filter.  Mind, this is a linear solution, not slew rate limiting per se.  Given the consistent, small signal level, this shouldn't make much difference.

I don't know what possible application you have though.

Tim

[Marco]

What can it cost? Maybe you could build something discrete with current steering into a capacitor with diode clamping and a fast follower, with enough effort.

If your time is precious and you don't need it for very long it might be efficient to just throw a ton of money at it and just rent an ultrafast waveform generator. If your time is precious and you do need it for a while it might be efficient to abuse some high speed DAC evaluation platforms to DIY an ultrafast waveform generator.

[jbb]

LVDS is current-fed, I think it’s +-4mA. So a ‘simple’ variable loading capacitor might be effective.

(4mA into 100R termination resistor makes about 400mV.)

M-LVDS transceivers are available which drive double current; they’re intended for use in busses with a resistor at each end. That means they drive 50R load and get similar voltage in the end.

[Marco]

LVDS is current-fed, I think it’s +-4mA. So a ‘simple’ variable loading capacitor might be effective.

Are there any which can do 10V/ns though?

That's more the domain of CML.

[David Hess]

A fast transconductance output driving a capacitor is one way.  If you want to go this route, take a look at the OPA860/OPA861 high bandwidth operational transconductance amplifier.

A higher performance option is a current biased diode bridge which can convert a fast transition time input into a controlled slew rate output up to 100s of MHz and higher by driving a capacitor.  This requires a high bandwidth voltage follower to buffer the output and this will ultimately limit performance, but we have some pretty fast buffers these days.  This circuit is more often seen protecting low impedance inputs and outputs from overload as shown below.

An alternative which might have worked in the past is a switched transconductance output from two complementary differential pairs, and Tektronix used this circuit sometimes, but it requires fast PNPs which are no longer available.  Tektronix used this up to 50 MHz.

[T3sl4co1l]

Note that a buffer is needed after the slew rate limiter, for gm or current source methods: the load is resistive, so any attempt to control drive current at the load side necessarily limits signal level (~300mV nominal) as well.  Or overdrives, as the case may be.  And buffering at such extreme slew rates will not be trivial.

Tim

[David Hess]

Note that a buffer is needed after the slew rate limiter, for gm or current source methods: the load is resistive, so any attempt to control drive current at the load side necessarily limits signal level (~300mV nominal) as well.  Or overdrives, as the case may be.  And buffering at such extreme slew rates will not be trivial.

I think the output buffer is the hardest part of the circuit.  An FET source follower with compensation to remove the Vgs offset by itself is not sufficient because it lacks a low enough output impedance, which means an FET source follower driving a bipolar output stage.  Luckily there are lots of integrated parts with sufficient performance now; the BUF802 which works exactly as I described looks interesting.

[T3sl4co1l]

And not just any FET -- 300mV at 10V/ns is 30ps.  Whether the source is even that fast to begin with, who knows.  It better be sharp, or amplification / clipping / sharpening will be needed, too.  BUF802 isn't even quite good enough.  (At least on paper -- though it looks like they weren't able to test it with a painfully fast signal, so it may perform better when driven harder.  I recall something like that being the case with the original "Damn Fast Buffer".)

Again, what purpose this is for, I have no idea.  And OP hasn't been forthcoming with more information.

Tim

[Marco]

An alternative which might have worked in the past is a switched transconductance output from two complementary differential pairs, and Tektronix used this circuit sometimes, but it requires fast PNPs which are no longer available.  Tektronix used this up to 50 MHz.

Can use a resistor to set the current, say 10V headroom for a sub 1V signal keeps the current constant enough.

A squarewave out of UHS logic if fast enough, otherwise ultrafast comparator or clock buffer, to drive a diode bridge to switch a current into a capacitor followed by an emitter follower and an ultrafast FDA to turn it into LVDS seems the way to go.

[David Hess]

And not just any FET -- 300mV at 10V/ns is 30ps.  Whether the source is even that fast to begin with, who knows.  It better be sharp, or amplification / clipping / sharpening will be needed, too.  BUF802 isn't even quite good enough.  (At least on paper -- though it looks like they weren't able to test it with a painfully fast signal, so it may perform better when driven harder.  I recall something like that being the case with the original "Damn Fast Buffer".)

The Fast and Damn Fast Buffer occurred to me also.  What kind of performance does a diamond buffer give with 4 GHz NPN and PNP transistors?  I never had access to a fast enough source to test one.

I would consider this more of a "best effort" kind of design.

A low input current buffer is not really needed, but again, fast PNP transistor are no longer available except in something like the BUF802.  What is the fastest unity gain, or x2 gain for that matter, integrated buffer available?  The BUF802 just caught my eye when I was looking through TI's list of parts.  I wasn't aware of it until I posted here.

A squarewave out of UHS logic if fast enough, otherwise ultrafast comparator or clock buffer, to drive a diode bridge to switch a current into a capacitor followed by an emitter follower and an ultrafast FDA to turn it into LVDS seems the way to go.

I know of several different ways to make fast pulse output stages with variable levels, but none of them implement variable slew rate without a linear output stage.

Oh, I thought of another way.  Implement a distributed output stage, lookup "distributed amplifier", with somehow a variable number of stages.  I guess the disabled stages could be biased into cutoff.  The output signal gets sharper as more stages are activated.  Hmm, distributed Ft doubler ...

[David Hess]

Distributed amplifiers gave me another idea.  Going back to the idea of using a varactor to make a variable RC section and varactors being very similar to step recovery diodes, configure a transmission line pulse shaper using varactors or step recovery diodes to make a variable edge rate.  The result is a Gaussian instead of Bessel response so very close to a slew rate limited edge.

This could be the easiest method, if it works, but it requires transmission line design techniques.

[EEEnthusiast]

LVDS is current-fed, I think it’s +-4mA. So a ‘simple’ variable loading capacitor might be effective.

(4mA into 100R termination resistor makes about 400mV.)

M-LVDS transceivers are available which drive double current; they’re intended for use in busses with a resistor at each end. That means they drive 50R load and get similar voltage in the end.

The real problem is that I need that slew rate to be programmable/tunable in-circuit. (Without changing the caps). How do I get a variable cap load which will work at those speeds is of concern.

[EEEnthusiast]

LVDS is current-fed, I think it’s +-4mA. So a ‘simple’ variable loading capacitor might be effective.

Are there any which can do 10V/ns though?

That's more the domain of CML.

No real world LVDS buffers does 10V/ns. But there is a clock input which I need to check out with a fast edge to check if there is any issue. It is a design verification.

[David Hess]

Before getting complicated, the simple solution alluded to earlier may be sufficient.  Use a common LVDS driver, which has a current output already, and install varactors directly at the output decoupled to ground.  Bias the varactors to high voltage minimizing the capacitance, and then lower the bias as needed to increase capacitance and decrease slew rate.

The capacitance of the varactors will create a source impedance mismatch but technically this does not matter if the other end of the transmission line is properly terminated.

[Marco]

The problem is the 100x range, that's just too much for whatever single stage solution. Voltage controlled low pass won't have the range, diode bridge will allow through too much driving signal at lower speeds etc etc.

You probably need two paths, 1V/ns-10V/ns and 0.1V-0.9V/ns and then add them up with a simple resistive combiner.

[David Hess]

Diode bridge will allow through too much driving signal at lower speeds etc etc.

From capacitive coupling?  Diode bridges have an awful lot of isolation.

[Marco]

I doubt it's even buildable without massive ringing even with 0201 components ... but in simulation at lower slewrate, the fast drive starts feeding through quite a bit. (The Schottky models are for BAT15, the slewrate is varied by changing R3/R4, which won't be trivial without hurting the high speed operation either.)

[David Hess]

Construction *will* be tricky, and limit performance.

An impedance of 47 kilohms is way too high.  Check the example I posted which operated up to 1 GHz with good analog performance.

[Marco]

A lower resistance would increase the current through the bridge and increasing the current increases the slew rate for the output, this is the resistance necessary for a low slew rate setting. Even if you could lower the rail voltage instead it wouldn't improve anything, you can put in an ideal current source and it still wouldn't improve.

As I said, a 100x range is quite large. Getting something which works both quite fast and quite slow is hard without going two path.

[David Hess]

A lower resistance would increase the current through the bridge and increasing the current increases the slew rate for the output, this is the resistance necessary for a low slew rate setting. Even if you could lower the rail voltage instead it wouldn't improve anything, you can put in an ideal current source and it still wouldn't improve.

The example I showed actively regulates the current while keeping the impedance fixed.  The circuit in the Tektronix 7A29 is more complicated than necessary because it corrects offset and input bias current also which was important in their application but not so much here.

[Marco]

Regardless, with a fixed input capacitance for the output buffer even 200 fF schottky's bleed through a little too much of the driving signal.

[David Hess]

Regardless, with a fixed input capacitance for the output buffer even 200 fF schottky's bleed through a little too much of the driving signal.

I thought that result looked amazingly good but I know it could be much better.  Like I said, the impedance biasing the diode bridge as shown is way too high.  A practical circuit uses much lower impedance and reactive correction for various effects.

You may be right that surface mount construction will not control the parasitic elements enough for it to work well enough.  Tektronix used hybrid construction and controlled impedance connections.

[T3sl4co1l]

Note that a chip component doesn't have lumped ESL and EPC and whatever, it has transmission line characteristics.

Down in the 50ps regime, even this distinction matters.

Corollary, everything you do must necessarily be done in a transmission line, with respect to its impedance, and accounting for any stub lengths, unterminated reflections, etc.

This is why I suggested a filtering approach over a conventional slew limiting approach.  Yes, as noted elsewhere, it will have a limited range, so needs to be done in multiple sections to cover the requested span.  That's not too terrible, I think; good RF switches exist.  Granted, I'm not sure the stub lengths in the filter itself, or in the switches, can even be low enough to get a good result.

Generating the initial edge rate, and verifying operation with a suitable probe and scope, are separate matters entirely.

It's just not a good problem, and all of this is damn good reason to question how/why it's a problem in the first place.

Tim