Electronics > Projects, Designs, and Technical Stuff

Small package decade counter?

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rcbuck:
Thanks Ian. I will test it late next week.

Ian.M:
For division ratios that are a multiple of four and are 16 or greater its even simpler - configure the PIC10F320 to use your signal as its system clock input and it will execute one instruction every four clock cycles so its just a matter of writing a program to toggle a pin with a delay in the loop to get the right division ratio:


--- Code: ---Loop:
   bsf LATA,0 ;Pulse RA0 on
   bcf  LATA,0 ;for four cycles
   ; delay goes here
   goto Loop ;(2 Tcy)

--- End code ---


Or for the squarewave version, which has a minimum division ratio of 24:

--- Code: ---Loop:
   bsf LATA,0 ;Pulse RA0 on
  ; delay goes here
   nop ; to match GOTO execution time
   nop
   bcf  LATA,0 ; and back off
   ; same delay goes here
   goto Loop ;(2 Tcy)

--- End code ---

Edit: although its standard midrange core it has a LATA SFR so code fixed to use it!

Benta:
Just use one of the cheap SO-8 divide-by-10 prescalers. Who cares if it's specified for 200 MHz, it will work anyway.

rcbuck:
Ian, is it possible for RA2 to feed both TMR0 and the CLC module?

Ian.M:
I wouldn't expect any issues with RA2 feeding both TMR0 and the CLC module, and still being readable as an input pin.  FIGURE 10-1: I/O PORT OPERATION in the datasheet indicates the feed to all the peripheral inputs is a straight tap-off from the input of the  PORTA read buffers, after the ANSELA gating.  Also there's nothing in the TIMER 0 or CLC sections to indicate that their inputs require exclusive use of the input pin.  Worst case: if I'm wrong, link RA2 and RA0 and feed the input to both of them then the CLC can use CL1IN0 on RA0 instead of CLC1IN1 on RA2..

Perhaps you are thinking of the PIC10F2xx families, which have a Timer 0 module tha takes exclusive use of GP2?

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