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Small signal DC unity gain buffer, avoiding overshoot

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stephanm:
When experimenting, I sometimes want to drive a stable DC voltage into some point of my circuit. Use cases are feeding ADCs or DACs with a reference voltage, changing biasing points in a circuit (by superimposing an external voltage on a node in a circuit throgh a resistor), supplying a VCO with a tuning voltage, simulating a voltage from a sensor on a circuit's input, etc.

An utility instrument for doing the above would be like a PSU, but with a low current output. For the overall construction, I was thinking of an ADC followed by an output stage, basically an unity gain voltage buffer. Leaving aside the voltage generator (ADC) part, I'd see the following requirements for the unity gain voltage buffer circuit:

- DC output voltage: -10V to +10V
- Offset voltage less than +/- 100uV
- No need for speed: settling times in the order of many 10's of milliseconds are OK
- Max output current for maintaining regulation: 10mA (sourcing and sinking)
- Max short circuit output current: max. 20mA (ideally for shorts to any external DC voltage between -30V and +30V)
- Stable with capacitive loads from 1pF to 50uF
- High impedance input (the driver in front of the output stage will likely be an op amp)
- Low AC output impedance
- No output capacitor
- As little overshoot/undershoot as possible, see below

I was simulating a few circuits in the past, and while I am not seeing an issue with most of the above requirements, I have some difficulties with the last point. My goal would be to have an output stage with only little under-/overshoot when the input voltage changes, but also when it recovers from short circuit or overload conditions. With "little", I mean less than, say, 200mV, i.e. low enough to not turn on ESD diodes in ICs. In a similar way, the requirement of having no output capacitor is meant to protect sensitive circuitry from seeing current spikes from my DC voltage generator when it's output capacitor discharges into the target circuit.

After having spent some many hours on this topic already, I'm no longer sure whether I have experimented with the wrong circuit topologies so far, or if I'm just overdoing my specs. Any comments or help will be appreciated.

From my experiments so far (read: simulations), the problem with overshoot/undershoot on recovery from shorts on the output can be boiled down to a situation that can already be seen in the circuit shown in the image. The resistors and diodes are meant for protecting op amp U1 in case of overload conditions. Note that it's clear to me that this circuit can have stability issues with capacitive loads and some DC issues as well. Also, don't take the component values too seriously, this circuit is just meant for discussion.

Suppose a load sinking 10mA is connected to DC_OUT while DC_IN=3V. Due to R1, the op amp's output voltage will be 4V, in order to compensate the 1V drop across R1. When the load current suddenly drops, for example to 1uA, DC_OUT will be at 4V until the op amp regulates it's output voltage back to DC_IN + 1uA*100 Ohms. So using the component values shown above, with this change of the load on DC_OUT the output will overshoot by 1V, more than what I wanted to have. Reducing R1 will help to lower the overshoot, but the price is a loss of protection when DC_OUT gets accidentially connected to some voltage beyond U1's supply voltages. Also, with a fast op amp for U1, the duration of the overshoot can be reduced, but what should be an upper limit in terms of time to play safe with sensitive circuitry connected to DC_OUT?

Another use case for such an output stage circuit would be buffering a precision voltage reference, such as an LM399. Here, the tradeoff I see is that the output stage would need to work for one input voltage only (DC_IN around 7V) while the offset voltage requirement would drop dramatically (stability of 1uV or better). For such a circuit, two feedback loops could be used, one for speed, and one for DC accuracy. However, that doesn't seem to make things simpler with respect to recovery from shorts or output overload :(

macaba:
Pulled this from my design archives, maybe have a play around in ltspice?
(developing intuition about circuits is what ltspice is best at!)
Try different compensation/op-amps though the values I have used are a good starting point.

stephanm:
Macaba, this circuit has exactly the issue I wanted to avoid. When you short circuit the output, the ADA4523 integrator goes all the way to V+ or V- and saturates. After removing the short, you get a huge voltage spike on the output (as low or high as the OP07 can go). It takes whatever time you're setting with your integrator R and C for the circuit to recover, with the given example values, that's several milliseconds. See below for a simulation, where the expected output voltage is 1V. The output gets shorted to ground at t=20ms, the short is removed at t=40ms.

One way to reduce the overshoot amplitude is to feed the OP07 with a weighted sum of the input voltage (V1) and the integrator output. This would maintain DC precision while reducing the overshoot.

macaba:
Easily solved... back-to-back low-leakage diodes over C1, adjust R3 to give you the current limit you want.
(Component references from my schematic)

macaba:
See attached, to avoid confusion. Output op-amp and various things changed to reduce the magnitude and duration of overshoot. (Now 100mV and tens of us in width)

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