I'm looking to do some hardware-based sniffing of communication between a USB 1.1 device and a host not under my control. There's a fair bit of info out there (openviszla, ultraembedded, lambdaconcept) when it comes to elaborate solutions involving FPGAs and possibly fast external memories for buffering USB HS data. That far exceeds my needs, so I'm looking for some advice for the path of least resistance.
It seems there's generally 2 approaches: using a USB PHY in non-driving mode which will unburden me from low level stuff like bit-stuffing and NRZI encoding. The alternative is to operate directly on the D+/D- signals. If possible I would implement this with only a microcontroller. For simplicitly the USB PHY seems preferable. It seems that all current USB PHY's support 480Mbps USB HS which is not necessarily beneficial to me. Such devices are clocked at 60MHz with an 8-bit databus (ULPI, i.e. USB3300) and there's also 16-bit versions implementing the UTMI interface which can run at 30MHz. I wonder if dealing with such a 60/30MHz bus will be problematic. Will I be able to sample and transmit data using a DMA transfer clocked by the PHY? Will I be able to react in time to changes on NXT, DIR and STP pins?
Another idea seems to be to use i.e. a STM32F405 with an external PHY, although I believe this only supports device, host and OTG roles. I just want the microcontroller to be a passive entity monitoring the data, remaining minimally stateful. This approach doesn't seem helpful, but perhaps I'm overlooking things here.
Any tips for either approach are welcomed.