EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: thexeno on May 28, 2021, 06:08:18 pm
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Hi, I am playing with a soft start feature, and I end up exploring the "stable multivibrator" variation shown in Dave's video (https://www.youtube.com/watch?v=Foc9R0dC2iI).
I don't understand why the latch starts in the ON state (PMOS fully on). Also in simulations. It looks like this:
[attachimg=2]
It seems that there is enough leakage from the PMOS body diode to let the NMOS gate "see" a voltage. Low leakage current from the PMOS body would explain the very long miller effect on the NMOS gate.
Am I right? Other interpretations? It can be solved by using a pulldown on the NMOS, but still this does not answer to my doubt.
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Your circuit is missing the capacitor.
Post the .asc file.
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I am not replicating the same circuit. This is only for turning on (hence my question).
The .asc attached had an additional switch to simulate the effect of turning off, since I wanted to turn it off from an external control signal. But please don't focus on that, it would be OT.
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I am not replicating the same circuit. This is only for turning on (hence my question).
The .asc attached had an additional switch to simulate the effect of turning off, since I wanted to turn it off from an external control signal. But please don't focus on that, it would be OT.
The .asc file you've posted starts with M5 off. I don't understand what you're trying to achieve.
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When you first apply power, the switch may come up in the on state. That's because of gate capacitance. When power is applied, the source of the P-channel mosfet comes up immediately, but the gate is still at ground, and its capacitance must be charged through the pullup resistor. During that brief time, the mosfet will turn on because Vgs is very high, and it may be on long enough to turn on the N-channel.
I think the solution would be to add a small capacitor in parallel with the gate pullup resistor. Then when power comes up, the capacitor would transfer the change in voltage to the gate, so the source and the gate would come up together, and the mosfet would stay off.
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The .asc file you've posted starts with M5 off. I don't understand what you're trying to achieve.
I am trying to understand why the latch starts in the ON state (PMOS fully on). What I am doing is part of another project (not simulated, did not bother to change naming of the mosfet, I think is not relevant - every new instance will increment the reference naming if I change the device characteristics every time). In this project, I wanted to put some controls like this, but I don't think is relevant for the question. Or am I missing something? To play safe, I attached again with the correct names.
When you first apply power, the switch may come up in the on state. That's because of gate capacitance. When power is applied, the source of the P-channel mosfet comes up immediately, but the gate is still at ground, and its capacitance must be charged through the pullup resistor. During that brief time, the mosfet will turn on because Vgs is very high, and it may be on long enough to turn on the N-channel.
I think the solution would be to add a small capacitor in parallel with the gate pullup resistor. Then when power comes up, the capacitor would transfer the change in voltage to the gate, so the source and the gate would come up together, and the mosfet would stay off.
This makes quite some sense. I will think through it later when I will get the chance to play with it again, and hopefully provide some results.
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First of all, as Zero999 wrote, you are missing the capacitor that holds M4 off during start-up, try adding it. Also, add a 10k pull-down resistor on the output (drain of M5), so it has some path to discharge.
Second, logic level Mosfets are not great for this kind of application, because they have pretty huge leakage and are hard to contorol. See the datasheet https://www.vishay.com/docs/73856/si4465ad.pdf (https://www.vishay.com/docs/73856/si4465ad.pdf)
SI4465 is a logic level TrenchFet with VGS(TH) as low as -0.45V and leakage of 1uA. Output capacitance of M4 could be enough to get it a bit open at the start. Lowering the R1 and adding a resistor between drain of M4 and v_net could also help.
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When you first apply power, the switch may come up in the on state. That's because of gate capacitance. When power is applied, the source of the P-channel mosfet comes up immediately, but the gate is still at ground, and its capacitance must be charged through the pullup resistor...
That is nonsense. The gate capacitance of P-channel (M5) is between it's gate and source. It doesn't have to be charged (or rather discharged), because it's already discharged. When Vbat rises, it's actually being divided between this M5's gate capacitance (something like 10nF) and the output capacitance of M4 (2nF).
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First of all, as Zero999 wrote, you are missing the capacitor that holds M4 off during start-up. Try adding it.
Thanks a lot - just to immediately address a possible miscommunication: when Zero999 mentioned the capacitor, I thought he meant the one of the other half of the circuit (in Dave's video, for debouncing).
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First of all, as Zero999 wrote, you are missing the capacitor that holds M4 off during start-up. Try adding it.
Thanks a lot - just to immediately address a possible miscommunication: when Zero999 mentioned the capacitor, I thought he meant the one of the other half of the circuit (in Dave's video, for debouncing).
Well, it is that capacitor, he probably thought it's connected to M4's gate. But you also need a pulldown on M5's drain, because the original circuit is using an NPN transistors and those don't have high impedance between base and emitter (gate and source) but FETs do.
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When you first apply power, the switch may come up in the on state. That's because of gate capacitance. When power is applied, the source of the P-channel mosfet comes up immediately, but the gate is still at ground, and its capacitance must be charged through the pullup resistor...
That is nonsense. The gate capacitance of P-channel (M5) is between it's gate and source. It doesn't have to be charged (or rather discharged), because it's already discharged. When Vbat rises, it's actually being divided between this M5's gate capacitance (something like 10nF) and the output capacitance of M4 (2nF).
Thanks very much for setting me straight in such a constructive way. So it would be your prediction that adding a small capacitor in parallel with the pullup resistor would not solve the problem? Well perhaps thexeno will have a chance to test that.
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I went through some thinking.
That is nonsense. The gate capacitance of P-channel (M5) is between it's gate and source. It doesn't have to be charged (or rather discharged), because it's already discharged. When Vbat rises, it's actually being divided between this M5's gate capacitance (something like 10nF) and the output capacitance of M4 (2nF).
Also, sorry for the confusion, the .asc file uploaded in the previous post contains my solution which so far is the most reliable with low Vth MOSFET. In fact, they have to work down to very low voltages, no only 3V so they have to be very low threshold.
I agree with the "nonsense" (in a friendly way obviously). A capacitor in parallel with the pullup won't change anything, because the cause was another.
The (simulated) reality is the very high sensitivity to voltages with NO loads whatsoever. Let's start with the test.asc attached.
In fact (and forgive me if I can't manage again to have a picture correctly inserted in the post), this is the simulation during the transient at rising vbat with the MOSFETs used in the previous asc simulations posted before:
[attach=1] (vth_too_low.jpg)
Despite the Vsg of PMOS is still zero, the gate is seeing a voltage and is getting charged (see Miller plateau), because the output (called n001) rises. I bet it is due to capacitive coupling source-drain of the PMOS.
With a PMOS with Vth = 2.8V the effect is dilated in time since the (unloaded) voltage on the n001 is lower, but eventually will still go on:
[attach=2] (pmos_2.8Vth.jpg)
Things are starting to differ when placing also an NMOS with Vth of 2.5V:
[attach=3] (nmos_2.5vth.jpg)
Because the n001 was going from a mid level between 0 and 3V, it was enough to make a positive feedback on the NMOS and turning all on. With the NMOS with higher threshold, is never enough to fully turn the NMOS on, and the n001 will settle in an intermediate, unloaded voltage.
To prove myself that it is a capacitive coupling or even the PMOS channel which is not pinched (and by pinched I mean it has the capability to provide a very low drain current, which immediately pinches the MOS channel if any load is applied), I tried to apply just a light load on n001:
[attach=4] (with_load.jpg)
Now, neither output load or higher thresholds are wanted, due to the nature of the low power I want to achieve. Hence, the solution that, in simulations, works reliably is draining away any parasitic voltage on the NMOS, which still uses a load, but it solved the issues on its root by pulling down the NMOS gate. This is in the final.asc file.
You can see the typical RC waveform which gets "dissipated" away, using a pulldown on the NMOS gate.
[attach=5] (working.jpg)
Let me know if my interpretations are making sense. or you have any suggestion/correction.
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No opinions? :)