Hello,
Consider this voltage "regulator" output stage. it is a part of a low noise regulator that is more like a reference instead of a regulator, as there is no error amplifier feedback system.

Quick brief description of the circuit:
V1 is the input supply. V2 is what sets the output voltage minus Vbe of Q1. R3 is a minimum load, and C2 is output capacitance for noise and stability.
Q1, Q2, Q3 form a szilaki pair with a pnp darlington pair, a hybrid of both. R4+R7 is for current balancing between Q2 and Q4.
R8, R5 is the basis of current limiting. if the voltage difference across R7 is enough to make Q5 start conducting, it means there is an overcurrent.
I am stuck on the next steps. How can I utilize this to reduce the voltage?
I tried attaching the collector to a N-MOSFET gate, and the drain to Q1 base, and source to GND. but this caused a lot of oscillations, which I am not sure how I can fix.
Would like to hear your opinions.
Thanks.