Author Topic: Soldermask Design for QFN and MLP(Q) Packages  (Read 4104 times)

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Offline jpanhaltTopic starter

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Soldermask Design for QFN and MLP(Q) Packages
« on: October 03, 2016, 09:19:59 am »
There are some previous posts that touch on this subject.  Here is one: https://www.eevblog.com/forum/projects/qfn-footprint-soldermask-between-pads-of-0-5-pitch-or-not/msg459850/#msg459850  However, I am not sure the conclusion there is applicable to my situation, as I plan to use hand soldering.

The chip (AS3935) is an MLPQ, which is very similar to the QFN.   It has 16 pins, is 4 mm x 4 mm, has 0.65 mm spacing, and has a central heatsink with ground plane connection.

One recommendation http://cds.linear.com/docs/en/packaging/Carsem] ([url]http://cds.linear.com/docs/en/packaging/Carsem MLP users guide.pdf )[/url] is to use "non solder mask defined" pads (NSMD pads). That is, don't put solder mask between the pads. The alternative is "solder mask defined pads" (SMD pads) which has each pad separated by a  line of solder mask. I understand the argument for using NSMD pads when doing reflow soldering.

Does anyone with experience have a recommendation for which type of solder mask to use for hand soldering?  It seems to me that with hand soldering the solder mask defined pad might be preferable as it should help avoid bridging under the chip.

My solder is 63/37 tin lead with rosin core.

John

 

Offline wraper

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #1 on: October 03, 2016, 09:53:39 am »
Depends on if it can be manufactured in the process you use. Cheap PCBs have serious limitations regarding if you can put solder mask in between the pads. If you want solder mask because of the solder bridging between the pads, adding solder mask to avoid the problem is a wrong answer. The right thing is to use smaller openings and thinner stencil to reduce the amount of solder paste transferred to the board.
 

Offline jpanhaltTopic starter

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #2 on: October 03, 2016, 10:03:13 am »
1) I most often go to Oshpark and have had no problems with its quality.
2) I don't use a stencil when hand soldering.

John
 

Offline wraper

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #3 on: October 03, 2016, 10:22:28 am »
1) I most often go to Oshpark and have had no problems with its quality.
it's not only about quality but design rules. Each manufacturer lists solder mask limitations. If you exceed them, then very likely your design will be rejected or solder mask between the pads will be removed by manufacturer without prior notice.
 

Offline zapta

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #4 on: October 03, 2016, 02:56:24 pm »
Never had problem with side mask between pads. IIRC Schwartz Boards (so?) patent is actually based on pad channels that make hand soldering easier.

Sometimes I make the pads longer to have better access for the solder tip.

In any case, flux is you friends when drag soldering small pitch smt. Just put enough of it and you will not have bridges.
 
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Offline jpanhaltTopic starter

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #5 on: October 03, 2016, 03:17:52 pm »
@zapta  Yes, "SchmartBoard" uses some type of channeling.   I believe the pads/lands may also be solder plated. I got a couple of its QFN boards (no heat sink), but the contacts extend too far under the chip.  Considered grinding them shorter, but decided to go with my own board and heat sink.

Thanks for the advice.   Completely agreed on flux -- it doesn't take much.

John
 

Offline jpanhaltTopic starter

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #6 on: October 03, 2016, 06:32:25 pm »
Here is a draft of my package in Eagle with adjustments for hand soldering. 
1)  I made the PCB pads the same width as the pads on the device;although, the standard for >= 0.65 spacing is to make them 0.05 mm wider (for <0.65 same width is recommended).  I extended the pads 1 mm beyond the outline to allow easy heating and soldering with my fine tip iron.
2)  Soldermask is at the default Eagle setting.
3)  The vias on the center pad are a result of recommendations to facilitate soldering.  Drill is 0.4 mm (Oshpark minimum is 0.33 mm).
4)  I made the center pad the size of the minimal, not nominal device pad for more clearance.

Note: I have not removed the construction lines yet.   I draw in DXF and import into the Eagle dimension layer.

Any comments on those adjustments?

Regards, John
« Last Edit: October 03, 2016, 06:36:16 pm by jpanhalt »
 

Offline zapta

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #7 on: October 04, 2016, 12:16:14 am »
If you want to solder the center tab from the back you may want to make the vias larger. I am not 100? sure. Others may comment.
 
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Offline T3sl4co1l

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #8 on: October 04, 2016, 02:53:26 am »
Drawing looks like an absolutely ordinary run-of-the-mill IPC-compliant QFN, to me.  Some manufacturers use weird names.

0.65mm pitch isn't a problem, even for Chinese fabs.  Use 4 mil (0.1mm) soldermask expansion, size the pad width equal to the pin width, and make sure there is enough soldermask web width (i.e., area where the soldermask actually is supposed to exist between the pads) that it won't flake off (minimum width 3 or 4 mils).

0.5mm pitch can get tricky, but it's okay to shave the pad width down slightly.

I've been told that good soldermask is a higher priority than precisely IPC-compliant pad sizes (which tend to be larger than necessary).

NSMD can be done, but that doesn't mean it should be done.  I have never seen it recommended.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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Offline jpanhaltTopic starter

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #9 on: October 04, 2016, 09:09:56 am »
@ T3sl4co1l
@zapta
Thanks for the reviews.I will check the soldermask extension past the pad.   I was thinking of making it smaller to help center the chip.   

zapta's comment about the via on the pad has me thinking about making that quite a bit larger.  The Schmartboard (schmartboard.com) breakout board is designed to help the small chips self center.   There are actual grooves for the leads/pads.  The center has a large via that is plated through.  It does not have a ring on the chip side.  The hole is about 1 mm or just a little smaller than the hole for a 25-mil square pin.  I think that design is to allow soldering of the exposed pad from below -- with or without a copper slug inserted -- to the bottom ground plane for heat conduction.

I extended the pads 1 mm past the chip.  Does that seem about right?

Regards, John
 

Offline T3sl4co1l

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Re: Soldermask Design for QFN and MLP(Q) Packages
« Reply #10 on: October 04, 2016, 09:47:42 am »
The pad extension (solder fillet toe -- check out IPC-7351A for terminology :) ) only needs to be 0.3mm for most anything.

If you're making these specifically for hand soldering, you may want more.  1mm seems excessive, but YMMV.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


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