SPI help

[Postal2]

You are talking about adding some extra resistance in the same order of the load that the tip capacitance presents at the x0MHz of SPI, ....

Yes, that's exactly it.

If you have a quartz crystal that has an unreliable start, you will never detect it by directly connecting the probe to its terminal - it will start at the moment you connect it. This is solved by connecting through a resistor (as well as doing it for adjusting the resonance of the coils with a trimmer core).
In the described case, resonance occurs - you need to use a resistor.

[Someone]

You are talking about adding some extra resistance in the same order of the load that the tip capacitance presents at the x0MHz of SPI, ....

Yes, that's exactly it.

If you have a quartz crystal that has an unreliable start, you will never detect it by directly connecting the probe to its terminal - it will start at the moment you connect it. This is solved by connecting through a resistor (as well as doing it for adjusting the resonance of the coils with a trimmer core).
In the described case, resonance occurs - you need to use a resistor.

For a crystal in a feedback loop the change in reactance by adding some comparable tip resistance may well produce a significantly different result, but that does not apply to general probing. Any tip resistor would need to be >>> the probe loading to make a substantial difference in the general case. An SPI line driver does not substantially change with reactance (while keeping impedance similar).

Better solution: have a selection of appropriate probes for different situations.

[Northy]

My ethernet device states this in the datasheet:

SCL is expected to stay low when SPI operation is idle. SPI operations start with the falling edge of SCS_N and end with
the rising edge of SCS_N. A single read or write access consists of a 27-bit command/address phase, then a 5-bit turnaround (TA) phase, then an 8-bit data phase. For burst read or write access, SCS_N is held low while SCL continues to
toggle. For every 8 cycles of SCL, the device will increment the address counter, and the corresponding data byte will
be transferred on SDI or SDO in succession.
All commands, addresses and data are transferred most significant bit first. Input data on SDI is latched on the rising
edge of clock SCL. Output data on SDO is clocked on the falling edge of SCL.

Is this mode 0?


My LCD device datasheet states this:

Only SPI mode 0 is supported.


So do I need the clk line transitioning half way through the data bit?

Thanks,

G

[Someone]

So do I need the clk line transitioning half way through the data bit?

Yes, that would be the first thing to check, that the data is stable around the sampling edge.... But...

My ethernet device states this in the datasheet:
.....
Input data on SDI is latched on the rising
edge of clock SCL. Output data on SDO is clocked on the falling edge of SCL.

and

My LCD device datasheet states this:

Only SPI mode 0 is supported.

Is this mode 0?

You tell us:
https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Mode_numbers
Ideally checking the timing diagrams in the data sheets rather than relying on mode "numbers".

[Siwastaja]

My ethernet device states this in the datasheet:

SCL is expected to stay low when SPI operation is idle. SPI operations start with the falling edge of SCS_N and end with
the rising edge of SCS_N. A single read or write access consists of a 27-bit command/address phase, then a 5-bit turnaround (TA) phase, then an 8-bit data phase. For burst read or write access, SCS_N is held low while SCL continues to
toggle. For every 8 cycles of SCL, the device will increment the address counter, and the corresponding data byte will
be transferred on SDI or SDO in succession.
All commands, addresses and data are transferred most significant bit first. Input data on SDI is latched on the rising
edge of clock SCL. Output data on SDO is clocked on the falling edge of SCL.

Is this mode 0?


My LCD device datasheet states this:

Only SPI mode 0 is supported.


So do I need the clk line transitioning half way through the data bit?

Thanks,

G

Yes, CLK line must transition half way through the data bit. The only question is whether 0->1 or 1->0 is the transition we talk about. Other transition happens simultaneously with data bit changing. That is the wrong transition.

After the polarity (half-cycle timing shift) is correct, then clock phase configuration is a shift of a full clock cycle. it isn't, see edit below

It is normal that slave devices are hard-wired to support only one mode. I would do the same as slave device designer. Change the clock polarity/phase configuration of SPI peripheral on the master side.

No one remembers the mode numbers and I have seen at least once if not twice that a datasheet specification does not match reality (manufacturer copy-pasted a wrong timing diagram etc.), so just go change CPOL (working on assumption that it is definitely wrong) and go through the remaining two modes (different CPHA) to find the one of the two which works.

Edit: Fuck, I got even the CPOL / CPHA names backwards compared to Wikipedia. If I do this mistake, I'm sure many others do it as well. So just test all four combinations until it works.

Edit 2: So from the Wikipedia table, it becomes obvious that swapping either one of the two bits swaps the sampling edge, they do not represent simply half-cycle and full-cycle delays like I initially wrote. So test all four combinations.

[Northy]

The ethernet chip has this timing diagram:

[Northy]

The LCD chip has no proper timing diagram 

[Siwastaja]

Pictures of layout or schematics would also help not only on question about signal integrity but also to understand they system. You have been talking about two SPI devices which sound like both are slaves. What is the master, and how the two slaves connect to the same bus, with two separate nCS signals, yes?

Does the communication to the ethernet chip always work and it's just the display which is failing? They might need different SPI mode, in which case you need to change the SPI peripheral configuration on the fly between accessing the two slaves (maybe disabling and re-enabling the SPI peripheral in-between), but that does not sound like a big problem.

This would be much easier with more information.

[ebastler]

...And of course, ignore Postal2 (I think it's obvious to most at this point?)

Did I stop you from giving a newbie the wrong directions?

Your technical advice is hit-or-miss and your attitude is consistently annoying. That's enough for me to enable "ignore user". 

[Postal2]

.... Better solution: have a selection of appropriate probes for different situations.

This is impossible. In some cases, when connecting the probe changes the operation of the device (as in this case), it is enough to connect a 10 cm long wire instead of the probe, holding it with insulated tweezers, including for starting the quartz. Therefore, it is customary to use a resistor in such cases. Of course, the signal obtained in this way is slightly distorted, but the question was precisely about how to view it.

Your technical advice is hit-or-miss and your attitude is consistently annoying. That's enough for me to enable "ignore user".

OK.

[dietert1]

It's impressive how after almost two pages of posts the clock/data timing relationship has not been verified. Unreliable data transmission with SPI is 99 % caused by wrong clock/data timing configuration and the other 1 % is clock out of spec (high). There is no way around checking the clock/data timing relationship. Stop trying to reduce the unreliability but fix it.

Regards, Dieter

Edit: And sorry, there is no SPI device without clock/data timing relationship specification. If you did not find it, you need to continue your search. You cannot and you did not setup the data transfer without that information.

[Siwastaja]

Unreliable data transmission with SPI is 99 % caused by wrong clock/data timing configuration

I only dared to say 90% but you are probably closer to truth.

[peter-h]

We're these people born geniuses or did they have to learn too?

They were born like that

The rest are just people copying/pasting from ChatGPT

It's impressive how after almost two pages of posts the clock/data timing relationship has not been verified.

Indeed. Checking this takes about 5 mins.

To the OP:



You can see the rising clock edge clocks in each data bit.

You can also see the CLK is parked HIGH (at the start and at the end) but that is not important. No idea why they draw it like that. In SPI it is normally parked LOW.

Some chips differ but they are unusual. This one (ADS1118) clocks the data on the falling edge



It also shows CLK parked LOW at the start, and parked HIGH at the end, just to sort the men from the sheep. All these chips run fine with the clock parked LOW. And if they didn't, there would probably be funny problems with the first packets after power-up.

How do you block somebody? Postal2 is a curious one. He posts after every post of mine, and the info, while in the right ballpark contextually, is nonsense.

[Pbtz]

It may not be the reason for the issues you're having, but it's usually good practice to insert a 22R or 33R series resistor in the output signals and perhaps limit the bandwidth of the net.

[Postal2]

...... is nonsense.

If you give a monkey glasses, it will put them on its butt.

[ebastler]

How do you block somebody?

Via the forum's main menu, go to Profile > Forum Profile;
then select Modify Profile > Buddies/Ignore List > Edit Ignore List.
There you can enter user names you want to "ignore".

You will still see their posts, but the posted text will be hidden. There is a "show me the post anyway" link instead, so you can still view the post if you are interested. I often do take a look, but then my expectation has been set and I have reminded myself that "this is a strange one, don't get upset". Works for me.

Users you are ignoring also can't send you Personal Messages via the forum. I have never encountered a situation where that was an effect I wanted/needed -- users who start to actively harrass others would be banned quickly anyway. But it's a side effect of the "ignore user" function which one apparently can't configure separately.

[Postal2]

.... usually good practice to insert a 22R or 33R series resistor in the output signals ....

It's hard to explain to people how strong resonance can be. And it happens precisely on the signal fronts, and it doesn't matter that the clock frequency is 5 MHz. Northy wanted to see this, and everyone should see this too.

[Someone]

.... Better solution: have a selection of appropriate probes for different situations.

This is impossible. In some cases, when connecting the probe changes the operation of the device (as in this case), it is enough to connect a 10 cm long wire instead of the probe, holding it with insulated tweezers, including for starting the quartz. Therefore, it is customary to use a resistor in such cases. Of course, the signal obtained in this way is slightly distorted, but the question was precisely about how to view it.

What does that 10cm wire achieve that a different probe could not? Electrically.

Probes are available with a wide range of load impedances, and I find it implausible that there are zero products which address your claimed fix of adding some hundreds of ohms in series (given some probes have exactly that by default!).

[Postal2]

What does that 10cm wire achieve that a different probe could not? ...

It is meant that touching critical points with a small piece of wire hanging in the air directly causes undesirable effects. In order for the oscilloscope probe not to cause such effects, the chip resistor must be at its end. I have not seen such probes, but I have seen a resistor soldered by the manufacturer with a tap to the measurement point many times (I hope everyone has seen it). Therefore, if the oscilloscope probe affects the circuit when connected, you can solder the chip resistor to the circuit and touch the probe through it. The choice of resistor value depends on the expected impedance of the circuit.

[dietert1]

In a well designed digital circuit there are no "critical points". 16 cm of wire are equivalent to 1 nsec. So unless the SPI is running at clock above 300 MHz, it won't be affected by a short piece of wire. Well designed digital circuits stay far away from any intricate analog effects. Unreliable operation like the OP reported indicates errors of the digital design.
Many programmable digital chips nowadays support "output pin drive strength" for EMI reasons. No need for external parts!

Regards, Dieter

[peter-h]

I think Postal2 is dropping in ChatGPT answers.

[inse]

I came late to the party and would like to know what kind of probe was used for the measurement.
10:1 >100Mhz with short ground connection?

[Siwastaja]

I think Postal2 is dropping in ChatGPT answers.

No, ChatGPT writing style is totally different and easily distinguishable from the annoying autistic verbosity.

Postal2 is an artistic experiment who is best ignored instead of replied to, but randomly maybe 20% of time happens to drop a sensible/correct comment.

But yeah, there is something similar with Postal2 and ChatGPT: tendency of hallucinating total random shit which makes no sense in any context. But writing style is totally different. Postal2 is a real person with brain wired up differently to the rest of us.

[Postal2]

In a well designed digital circuit there are no "critical points". ...

I just bought an mp3 player board with an unstable quartz crystal that even senses touch on the case.
https://www.eevblog.com/forum/projects/diy-mp3oggflac-player-feasible/msg5681177/#msg5681177
You can have a good design, but the component will let you down.

I came late to the party and would like to know what kind of probe was used for the measurement.
10:1 >100Mhz with short ground connection?

I recently checked the MIPI DSI CLK frequency, which was 200 MHz, with a Micsig oscilloscope and the included ~200 MHz probes. The scope showed about 50 mV amplitude from one of the differential outputs relative to ground. However, I had to turn off all the lights except the incandescent ones to see it.

I think Postal2 is dropping in ChatGPT answers.

I usually hear the word "ChatGPT" from stupid people, I have never tried it, but I actually attended a XILINX seminar about AI and I know how it works.

[dietert1]

In a well designed digital circuit there are no "critical points". ...

I just bought an mp3 player board with an unstable quartz crystal that even senses touch on the case.
https://www.eevblog.com/forum/projects/diy-mp3oggflac-player-feasible/msg5681177/#msg5681177
You can have a good design, but the component will let you down.
...

A crystal oscillator is an analog circuit. SPI data transfer is a digital circuit.

Regards, Dieter